Silicon-On-Insulator (SOI) Technology

Manufacture and Applications

O. Kononchuk, B.-Y. Nguyen

• Publisher: Woodhead Publishing
• Year: 2014
• Print ISBN:
  9780857095268
• eBook ISBN:
  9780857099259
• Topic: Technology & Engineering
• Subtopic: Materials Science
• Index: Technology & Engineering

Silicon-On-Insulator (SOI) Technology: Manufacture and Applications covers SOI transistors and circuits, manufacture, and reliability. The book also looks at applications such as memory, power devices, and photonics. The book is divided into two parts; part one covers SOI materials and manufacture, while part two covers SOI devices and applications. The book begins with chapters that introduce techniques for manufacturing SOI wafer technology, the electrical properties of advanced SOI materials, and modeling short-channel SOI semiconductor transistors. Both partially depleted and fully depleted SOI technologies are considered. Chapters 6 and 7 concern junctionless and fin-on-oxide field effect transistors. The challenges of variability and electrostatic discharge in CMOS devices are also addressed. Part two covers recent and established technologies. These include SOI transistors for radio frequency applications, SOI CMOS circuits for ultralow-power applications, and improving device performance by using 3D integration of SOI integrated circuits. Finally, chapters 13 and 14 consider SOI technology for photonic integrated circuits and for micro-electromechanical systems and nano-electromechanical sensors. The extensive coverage provided by Silicon-On-Insulator (SOI) Technology makes the book a central resource for those working in the semiconductor industry, for circuit design engineers, and for academics. It is also important for electrical engineers in the automotive and consumer electronics sectors. - Covers SOI transistors and circuits, as well as manufacturing processes and reliability - Looks at applications such as memory, power devices, and photonics

Part I

Silicon-on-insulator (SOI) materials and manufacture

Outline

1 Materials and manufacturing techniques for silicon-on-insulator (SOI) wafer technology

2 Characterization of the electrical properties of advanced silicon-on-insulator (SOI) materials and transistors

3 Modeling the performance of short-channel fully depleted silicon-on-insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs)

4 Partially depleted (PD) silicon-on-insulator (SOI) technology: circuit solutions

5 Planar fully depleted (FD) silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology

6 Silicon-on-insulator (SOI) junctionless transistors

7 Silicon-on-insulator (SOI) fin-on-oxide field effect transistors (FinFETs)

8 Understanding variability in complementary metal oxide semiconductor (CMOS) devices manufactured using silicon-on-insulator (SOI) technology

9 Protecting against electrostatic discharge (ESD) in complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) manufactured using silicon-on-insulator (SOI) technology

1

Materials and manufacturing techniques for silicon-on-insulator (SOI) wafer technology

H. Moriceau and F. Fournel, CEA, LETI, France

F. Rieutord, CEA, INAC, France

Abstract:

This chapter reviews various processes for manufacturing SOI wafers. There is a specific focus on Separation by IMplantation of OXygen (SIMOX) and on technologies based on direct bonding (bonded silicon-on-insulator (BSOI), epitaxial layer transfer process (Eltran®), Smart Cut™). For the latter, the physical and chemical properties of both starting wafers and SOI structures are mainly discussed. These analyses help in developing models for direct bonding and splitting. Recent fabrication process improvements and trends towards innovative engineered structures are also described.

Key words

SOI; ion implantation; direct bonding; thinning down processes; wafer manufacturing

1.1 Introduction

SOI structures consist of a top single-crystal silicon layer, either separated from the bulk substrate by an insulating layer (for instance SiO₂) or directly supported by an insulating substrate.^1–5

Technologies based on the use of a buried oxide layer, SiO₂, as an insulator in SOI wafers have been widely developed in microelectronics because of their advantages compared to silicon bulk substrates. Among other benefits, SOI wafers allow:

• lower parasitic device capacitances due to isolation from the bulk silicon substrate, which results in lower power consumption

• higher speed devices, avoiding latchup effects due to a complete isolation of the n- and p-well devices

• radiation-hardening for sensitive applications.

SOI wafers are used in microelectronics, the fabrication of microelectromechanical systems (MEMS), photonics and biotechnological chips. As an example, the mechanical properties of single-crystal Si films are superior to those of polycrystalline films. This makes them a better choice for the fabrication of MEMS components. The buried oxide layers in SOI structures also facilitate fabrication of MEMS devices. In photonic applications, the high contrast of refractive indices between Si and SiO₂ in SOI wafers allows efficient photon confinement in small waveguides with sharp bends.

From an industrial point of view, SOI substrates are compatible with most conventional device fabrication processes in microelectronics. This means that most SOI-based processes may be carried out in an existing factory built for conventional Si device fabrication. Devices made using SOI structures differ from conventional devices using bulk silicon. SOI structures are built above electrical insulators, typically using silicon dioxide, silicon nitride, diamond or sapphire.⁶ Such electrical insulators may be either buried layers or bulk wafers. The choice of insulator material depends largely on the application. As an example, one might choose:

• silicon dioxide to obtain decreased short channel effects in microelectronics devices;

• diamond to allow thermal dissipation if needed to deal with the self-heating effect; or

• sapphire for high-performance radio frequency applications.

1.2 SOI wafer fabrication technologies: an overview

This section provides an overview of the diverse technologies developed to fabricate SOI wafers. It will concentrate on SIMOX, BSOI, Eltran® and Smart Cut™ technologies, which have allowed industrial-volume production of SOI structures, including buried insulating SiO₂ layers.

Since the 1970s, several novel techniques for fabricating SOI wafers have been explored and developed.⁵ These have included silicon epitaxial growth onto single-crystal substrates such as sapphire,⁷ zirconia⁸ or seeded silicon wafers. Silicon-on-sapphire (SOS) structures are still made by this technique, although the quality of the silicon layers remains one of the main concerns. Silicon epitaxial lateral overgrowth (ELO) techniques⁹ were developed as alternatives, in which growth occurs from holes in the oxide layer of an oxidized Si wafer and expands laterally over that layer. These approaches were limited because they did not allow very large areas of overgrowth.

At the same time, techniques were explored that were based on the rapid melting by laser or hot wire heating of a polysilicon layer deposited onto SiO₂ layers followed by controlled crystallization.^10–12 These techniques were unsuccessful because of the poor quality of the crystallized silicon.

In the early 1980s, the full isolation with porous oxidized silicon (FIPOS) method was developed. This involved the oxidation of porous regions below non-porous islands of Si, in order to form local SOI.^13–15 However, the wafer patterning required was a problem, and FIPOS was abandoned when SIMOX and direct bonding processes became available.

SIMOX technologies...

Table of contents

• Cover image
• Title page
• Table of Contents
• Copyright
• Contributor contact details
• Woodhead Publishing Series in Electronic and Optical Materials
• Introduction
• Part I: Silicon-on-insulator (SOI) materials and manufacture
• Part II: Silicon-on-insulator (SOI) devices and applications
• Index