Computer Hardware Description Languages and their Applications

Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications - CHDL '93 Sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC, Ottawa, Ontario, Canada, 26-28 April, 1993

D. Agnew, L. Claesen, R. Camposano, D. Agnew, L. Claesen, R. Camposano

• Publisher: North Holland
• Year: 2014
• Print ISBN: 9780444816412
• eBook ISBN: 9781483298023
• Topic: Computer Science
• Subtopic: Operating Systems
• Index: Computer Science

Hardware description languages (HDLs) have established themselves as one of the principal means of designing electronic systems. The interest in and usage of HDLs continues to spread rapidly, driven by the increasing complexity of systems, the growth of HDL-driven synthesis, the research on formal design methods and many other related advances.This research-oriented publication aims to make a strong contribution to further developments in the field. The following topics are explored in depth: BDD-based system design and analysis; system level formal verification; formal reasoning on hardware; languages for protocol specification; VHDL; HDL-based design methods; high level synthesis; and text/graphical HDLs. There are short papers covering advanced design capture and recent work in high level synthesis and formal verification. In addition, several invited presentations on key issues discuss and summarize recent advances in real time system design, automatic verification of sequential circuits and languages for protocol specification.

Table of contents

• Front Cover
• Computer Hardware Description Languages and Their Applications
• Copyright Page
• Table of Contents
• Preface
• Conference Organization
• "Real Time Distributed Systems (invited presentation)" Mario R. Barbacci, Carnegie Mellon University
• Real-time Distributed Systems
• Session : BDD-based Design and Analysis Techniques chair: Luc Claesen
• Verification of the Futurebus+ Cache Coherence Protocol*
• Chapter 03."Exploiting Symbolic Traversal Techniques for Efficient Process Algebra Manipulation"
• Chapter 04."Hardware- Verification using First Order BDDs "
• Session: HDL-based Design Methods chair: Franz Rammig
• Chapter 05."HW/SW Co-Design with PRAMs Using CoDES"
• Chapter 06."Prevail-DM: A Framework-Based Environment for Formal Hardware Verification "
• Chapter 07."Better Verification Through Symmetry"
• Session: Synthesis and Verification chair: Mario Barbacci
• Chapter 08."A Rewriting Based Method for the Formal Verification of Microprocessors"
• Chapter 09."Reasoning about the VHDL Standard Logic Package Signal Data Type "
• Chapter 10."An Efficient Data-Path Synthesis Based on Algorithmic Description under the Constraints of Time and Area"
• Chapter 11."Integrating Boolean Verification with Formal Derivation"
• Chapter 12."Automated High-level Verification Against Clocked Algorithmic Specifications"
• Chapter 13."The Backward Walk Approach in FSM Verification"
• Invited Presentation : Automatic Verification of Sequential Circuit Designs Edmund M. Clarke, Carnegie Mellon University
• Automatic Verification of Sequential Circuit Designs
• Session: Protocol Specification chair: Ed Cerny
• Chapter 14."Toward a Basis for Protocol Specification and Process Decomposition "
• Chapter 15."Integrating SDL and VHDL for System-Level Hardware Design"
• Session:Formal Reasoning about Regular Structures chair: Carlos Delgado Kloos
• Chapter 16. Reasoning About Array Structures Using a Dependently Typed Logic
• Chapter 17."VHDL Description and Formal Verification of Systolic Multipliers"
• Chapter 18.Transformational Rewriting with Ruby
• Session: High Level Synthesis chair: Flavio Wagner
• Chapter 19."A Representation for the Binding of RT-Component Functionality to HDL Behavior"
• Chapter 20."Performance Specification and Measurement"
• Chapter 21."Automatic Synthesis of Sequential Synchronizations"
• Session:Design Capture chair: Edmund M. Clarke
• Chapter 22."Specifying Hardware Systems in LOTOS"
• Chapter 23."HML: A Hardware Description Language Based on Standard ML"
• Chapter 24."An Efficient Object-Oriented Variation of the Statecharts Formalism for Distributed Real-Time Systems"
• Chapter 25."Linking System Design Tools and Hardware Design Tools
• Chapter 26."Automatic VHDL Model Generation System"
• Chapter 27.Automatic VHDL Model Generation System
• Chapter 28."The Modeler's Assistant: A CAD Tool for Behavioral Model Development"
• Chapter 29."Insulin: An Instruction Set Simulation Environment"
• "Specification languages for communication protocols (invited presentation)"
• Session: Timing Specifications in HDLs chair: John Brzozowski
• Chapter 30."Integrating Behavior and Timing in Executable Specifications"
• Chapter 31."ESP: An Executable Specification Language for Mixed Timing Control Circuits "
• Session:Textual and Graphical HDLs chair: Robert Hum
• Chapter 32."UDL/I version Two: A New Horizon of HDL Standards"
• Chapter 33."Verilog HDL Modeling Styles for Formal Verification"
• Chapter 34."A Visual Hardware Description Language "
• Chapter 35."Textual/Graphical Design Concept-Level Synthesis"
• Sessions : VHDL
• Chapter 36."System-Level Specification and Design Using VHDL: A Case Study"
• Chapter 37."A Denotational Definition of the VHDL Simulation Kernel"
• Chapter 38."Checking DFT Rules with a VHDL Simulator"
• Chapter 39."Parameterized VHDL entities for the simulation of hybrid circuits"
• Chapter 40."Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models"
• Chapter 41."Analog-VHDL: As an application, a real example"