1.2.1 Mooreâs Law, More Than Moore, and Beyond Moore Challenges and Sustainability
It is very important to distinguish Mooreâs law from individual device and geometrical scaling. Mooreâs law was based on economic considerations regarding the historical trend on the multiplication by 2 every year of the number of devices âcrammed on a chipâ [1]. Such a statement automatically implies a reduction of the cost per function. Moore mentioned that the trend would be pursued in the future. At that time, bipolar transistors were the most advanced active devices of an integrated circuit. The microelectronics business had not adopted MOSFETs (metal oxide semiconductor field effect transistors) yet. MOSFET became popular around 1970 [2] while beliefs predicted its fading progress by the end of the 1970s! Actually, no geometrical scaling rule of MOSFET was clearly established before Dennard et al.âs work [3] on scaling, taking advantage of self-aligning source and drain doping by ion implantation on a polysilicon gate.
The historical trend had been followed naturally until the beginning of the 1990s. The evolution was agreed to be sustainable, when the US National and the International Technology Roadmap for Semiconductors (ITRS) edited the first coordinated roadmaps. The semiconductor equipment suppliers and end users requested integrated device manufacturers to âsit around a tableâ and discuss about objectives, well documented and realistic roadmaps [4, 5] (Fig. 1.1). It took a while to select the good benchmarkers while microelectronics kept gaining in maturity. The main guideline approved by the roadmap working groups was the geometrical scaling of CMOS and memories based on the MOSFET technology [6]. Bipolar devices, associated with CMOS in BiCMOS schemes, were still dominating in the RF (radio frequency) business. Thanks to the success of MOSFET technology, the number of transistors in dynamic memories and microprocessor circuits surpassed 1 billion as early as 1995 [7] and 2006 [8], respectively. CMOS scaling is based on a list of geometrical rules that establish, in fine, the resulting electrical characteristics, power consumption, and performance of devices. The ITRS identified three main families of devices, linked to the major categories of products that the industry would be delivering: high performance (HP), low operating power (LOP), and low standby power (LSTP) device architectures were defined. Meanwhile, three domains were defined by the European MEDEA initiative, depending on their maturity, pervasiveness, specificity to applications, or aptitude to scaling: they first defined the domains more Moore and more than Moore, which distinguished, respectively, CMOS (linearly scalable) and the devices that were more application oriented and likely to improve the diversification of integrated circuits and systems. The more than Moore devices domain defines a category including sensors and actuators, memories, RF devices and passives, power/high voltage devices, bioelectronic devices, and so on [4] (Fig. 1.2). In parallel, various types of devices that could challenge CMOS either in their ultimate configuration or by using a state variable different from electric charge have been investigated. The so-called Beyond CMOS or Beyond Moore domain lists the features of these devices by systematically benchmarking their progress or maturity year after year. After gaining in maturity, some of them might enter a transition table before being considered for the roadmap. That was the case for FinFET or multigate devices before their introduction into the roadmap tables. Magnetic random-access memories (MRAMs) and particularly ...