Computer Organization

Basic Processor Structure

James Gil de Lamadrid

• Editorial: Chapman and Hall/CRC
• Año: 2018
• ISBN:
  9781351999748
• Edición: 1
• Categoría: Informatik
• Categoría: Systemarchitektur

Computer Organization: Basic Processor Structure is a class-tested textbook, based on the author's decades of teaching the topic to undergraduate and beginning graduate students. The main questions the book tries to answer are: how is a processor structured, and how does the processor function, in a general-purpose computer?

The book begins with a discussion of the interaction between hardware and software, and takes the reader through the process of getting a program to run. It starts with creating the software, compiling and assembling the software, loading it into memory, and running it. It then briefly explains how executing instructions results in operations in digit circuitry. The book next presents the mathematical basics required in the rest of the book, particularly, Boolean algebra, and the binary number system.

The basics of digital circuitry are discussed next, including the basics of combinatorial circuits and sequential circuits. The bus communication architecture, used in many computer systems, is also explored, along with a brief discussion on interfacing with peripheral devices. The first part of the book finishes with an overview of the RTL level of circuitry, along with a detailed discussion of machine language.

The second half of the book covers how to design a processor, and a relatively simple register-implicit machine is designed. ALSU design and computer arithmetic are discussed next, and the final two chapters discuss micro-controlled processors and a few advanced topics.

Contents

Introduction and Remarks

CHAPTER 1 ▪ Overview

1.1 HIGH-LEVEL, ASSEMBLY, AND MACHINE LANGUAGES

1.1.1 High-Level Languages

1.1.2 Machine Language

1.1.3 Assembly Language

1.2 COMPILERS AND ASSEMBLY LANGUAGE

1.2.1 Assembly Language Translation

1.2.2 The Translation Process

1.3 THE ASSEMBLER AND OBJECT CODE

1.3.1 External References

1.3.2 Compiler versus Assembler

1.4 THE LINKER AND EXECUTABLE CODE

1.4.1 Resolving External References

1.4.2 Searching Libraries

1.4.3 Relocation

1.5 THE LOADER

1.5.1 Processes and Workspaces

1.5.2 Initializing Registers

1.6 SUMMARY OF THE TRANSLATION PROCESS

1.7 THE PROCESSOR

1.7.1 Processor Behavior

1.7.2 Processor Structure

1.7.2.1 The Data Path, Registers, and Computational Units

1.7.2.2 Control Circuitry

1.8 DIGITAL CIRCUITRY

1.9 SUMMARY

1.10 EXERCIES

CHAPTER 2 ▪ Number and Logic Systems

2.1 NUMBERS

2.1.1 Hexadecimal Numbers

2.1.2 Adding Binary Numbers

2.1.3 Representing Negative Integers

2.2 BOOLEAN ALGEBRA

2.2.1 Boolean Functions

2.2.2 Boolean Expressions and Truth Tables

2.2.3 Don’t Care Conditions

2.2.4 Boolean Simplification Using Identities

2.2.4.1 Boolean Identities

2.2.4.2 DeMorgan’s Law

2.2.4.3 Simplifying the XOR Function

2.2.4.4 Example Simplification Using Identities

2.2.5 Boolean Simplification Using Karnaugh-Maps

2.2.5.1 K-Map for Functions of Two Variables

2.2.5.2 K-Maps for Functions of Three Variables

2.2.5.3 K-Maps for Functions of Four Variables

2.2.5.4 Don’t Care Conditions in Karnaugh-Maps

2.2.5.5 K-Maps for Functions of More than Four Variables

2.3 SUMMARY

2.4 EXERCISES

CHAPTER 3 ▪ Digital Circuitry

3.1 COMBINATIONAL CIRCUITS

3.1.1 Designing with Logical Gates

3.1.2 Common Combinational Circuits

3.1.2.1 The Decoder

3.1.2.2 The Encoder

3.1.2.3 The Multiplexer

3.1.2.4 MUX Composition

3.1.2.5 The Adder

3.1.2.6 The Ripple-Carry Adder

3.2 SEQUENTIAL CIRCUITS

3.2.1 The Clock

3.2.2 Storage Devices

3.2.2.1 The D-Type Storage Devices

3.2.2.2 The D-Latch

3.2.2.3 The D-Flip-Flop

3.2.2.4 The J-K- Storage Device

3.2.2.5 Flip-Flops with Extra Pins

3.2.3 Sequential Design

3.2.3.1 The FSM and State Diagrams

3.2.3.2 The FSM and the State Transition Table

3.2.3.3 State Diagrams and Transition Tables: Building One Representation from the Other

3.2.3.4 Moore versus Mealy Machines

3.2.3.5 Implementing a Sequential Design

3.2.4 Sequential Circuit Analysis

3.2.5 Common Sequential Circuits

3.2.5.1 The Parallel-Load Register

3.2.5.2 The Shift Register

3.2.5.3 The Counter

3.2.5.4 The Standard Register

3.3 SUMMARY

3.4 EXERCISES

CHAPTER 4 ▪ Devices and the Bus

4.1 MEMORY

4.1.1 Memory Operation

4.1.2 Memory Types: ROM and RAM

4.1.3 Memory Composition

4.1.3.1 Horizontal Composition

4.1.3.2 Vertical Composition

4.1.4 Internal Memory Structure

4.1.5 RAM Types

4.1.6 ROM Types

4.1.7 Word and Byte Addressing

4.1.8 Machine Byte Order

4.2 PERIPHERAL DEVICES

4.2.1 Peripheral Device Types

4.2.2 Device Polling

4.2.3 Interrupts

4.3 THE CPU

4.4 BUS COMMUNICATION

4.4.1 Bus Structure

4.4.2 Bus Addressing

4.4.3 Bus Addressing Example

4.5 SUMMARY

4.6 EXERCISES

CHAPTER 5 ▪ The Register Transfer Language Level

5.1 MICRO-INSTRUCTIONS AS CIRCUITS

5.1.1 RTL Design

5.1.2 A Larger Example

5.1.3 RTL Analysis

5.1.4 Transforming a Structural Description into a Behavioral Description

5.1.5 Problems with Reverse Engineering

5.2 COMMON PROCESSOR MICRO-INSTRUCTIONS

5.2.1 RTL Descriptions of Combinational Circuits

5.2.2 RTL Descriptions of Sequential Circuits

5.2.3 Processor Micro-Operations

5.2.3.1 Arithmetic Micro-Operations

5.2.3.2 Logic Micro-Operations

5.2.3.3 Shift Micro-Operations

5.2.3.4 Memory Access Micro-Operations

5.3 ALGORITHMIC MACHINES

5.3.1 The Teapot Example

5.3.2 Generating a Flowchart, and the Role of the Sequencer

5.3.3 Generating RTL from the Flowchart

5.4 RTL AND VERILOG

5.5 SUMMARY

5.6 EXERCISES

CHAPTER 6 ▪ Common Computer Architectures

6.1 INSTRUCTION SET ARCHITECTURE

6.1.1 Data Transfer

6.1.1.1 Register-to-Register Transfer

6.1.1.2 Register-to-Memory Transfer

6.1.1.3 Memory-to-Register Transfer

6.1.1.4 Device Transfer

6.1.2 Data Manipulation Instructions

6.1.2.1 Common Data-Types

6.1.2.2 The Integer Data-Type

6.1.2.3 The Real Data-Type

6.1.2.4 The Boolean Data-Type

6.1.2.5 The Character Data-Type

6.1.2.6 Binary Coded Decimal

6.1.2.7 Data Manipulation Operation Types

6.1.2.8 Arithmetic Operations

6.1.2.9 Logic Operations

6.1.2.10 Shift Operations

6.1.3 Control Operations

6.1.3.1 Unconditional Branches

6.1.3.2 Conditional Branches

6.1.3.3 Machine Reset Instructions

6.1.3.4 Context Manipulation Instructions

6.2 INSTRUCTION FORMAT

6.3 ADDRESSING MODES

6.3.1 Direct Mode

6.3.2 Indirect Mode

6.3.3 Register Direct Mode

6.3.4 Register Indirect Mode

6.3.5 Immediate Mode

6.3.6 Implicit Mode

6.3.7 Relative Mode

6.3.8 Indexed Mode

6.3.9 Addressing in Machine Language

6.4 ALTERNATE MACHINE ARCHITECTURES

6.4.1 The Register Machine

6.4.1.1 Register Machine Instruction Format

6.4.1.2 Register Machine Programming Example

6.4.2 The Register Implicit Machine

6.4.2.1 Register Implicit Machine Instruction Format

6.4.2.2 Register Implicit Machine Programming Example

6.4.3 The Accumulator Machine

6.4.3.1 Accumulator Machine Instruction Format

6.4.3.2 Accumulator Machine Programming Example

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