Memory Address Register

3 Key excerpts on "Memory Address Register"

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  eBook - ePub

  Computer Architecture and Security

  Fundamentals of Designing Secure Computer Systems

  • Shuangbao Paul Wang, Robert S. Ledley(Authors)
  • 2012(Publication Date)
  • Wiley

    (Publisher)

  Registers are used in many different ways in a computer. One can be used to hold the address of current instruction being executed. It is called program counter register (PC). The instruction register (IR) holds the actual instruction being executed currently by the computer. The status register holds several 1-bit registers and each one keeps track of special conditions of the CPU. The flags contain information such as arithmetic carry, negative sign, overflow and other critical information that is monitored by the control unit.

  Memory, or random access memory (RAM) can be individually accessed in a random manner. A computer memory system usually contains billions of single 1-bit memory units. In order to access those memory units, a processor uses two registers: Memory Address Register (MAR) and memory data register (MDR) (Foster and Iberall, 1985). Sometimes a memory data register is referred to as a memory buffer register as it holds the data that is being stored or retrieved from the memory location currently addressed by the Memory Address Register.

  Figure 3.5 shows the relationship between the MAR, MDR and memory. An address decoder is used to reduce the number of addresses required for the large number of memory units. For example, a 32-bit address bus can address 232 = 4G memory.

  Figure 3.5 The relationship between the MAR, MDR, and memory

  In MAR, the highest bit called most significant bit (MSB) and the lowest bit called the least significant bit (LSB) (Randell, 1982). In MDR, the number of bits that can be accessed at the same time is determined by the width of the register that is connected to the processor. For a 32-bit data bus, one instruction can process 32-bit data. While 64-bit data can be processed within one instruction for a 64-bit data bus. So generally speaking a 64-bit computer is faster.

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  eBook - PDF

  Fundamentals of Computer Organization and Architecture

  • Hesham El-Rewini, Mostafa Abd-El-Barr(Authors)
  • 2005(Publication Date)
  • Wiley-Interscience

    (Publisher)

  5.2.1. Memory Access Registers Two registers are essential in memory write and read operations: the memory data register (MDR) and Memory Address Register (MAR). The MDR and MAR are used exclusively by the CPU and are not directly accessible to programmers. In order to perform a write operation into a specified memory location, the MDR and MAR are used as follows: 1. The word to be stored into the memory location is first loaded by the CPU into MDR. 2. The address of the location into which the word is to be stored is loaded by the CPU into a MAR. 3. A write signal is issued by the CPU. Similarly, to perform a memory read operation, the MDR and MAR are used as follows: 1. The address of the location from which the word is to be read is loaded into the MAR. 5.2. REGISTER SET 85 2. A read signal is issued by the CPU. 3. The required word will be loaded by the memory into the MDR ready for use by the CPU. 5.2.2. Instruction Fetching Registers Two main registers are involved in fetching an instruction for execution: the pro- gram counter (PC) and the instruction register (IR). The PC is the register that con- tains the address of the next instruction to be fetched. The fetched instruction is loaded in the IR for execution. After a successful instruction fetch, the PC is updated to point to the next instruction to be executed. In the case of a branch operation, the PC is updated to point to the branch target instruction after the branch is resolved, that is, the target address is known. 5.2.3. Condition Registers Condition registers, or flags, are used to maintain status information. Some architec- tures contain a special program status word (PSW) register. The PSW contains bits that are set by the CPU to indicate the current status of an executing program. These indicators are typically for arithmetic operations, interrupts, memory protection information, or processor status.

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  eBook - PDF

  Computer Systems Architecture

  • Aharon Yadin(Author)
  • 2016(Publication Date)
  • Chapman and Hall/CRC

    (Publisher)

  222 ◾ Computer Systems Architecture starts execution, the operating system loads the base register, and each memory access is calculated by adding the content of the register to the displacement defined in the instruc-tion. In this way, it is possible to access a very large address space and to maintain control of the instruction sizes. Calculating the real address is done by the MMU for each memory access, and it includes a simple addition of the logical address that appears in the instruction and the base register ( Figure 5.30 ). The principle that led to this addressing mode is locality of reference, which is also responsible for the hierarchical memory architecture already discussed. This locality of reference, which will be further elaborated on in Chapter 6 , “Cache Memory,” means that when a program is executed, most of the time it will use items of data that are close to each other and the instructions for which are in close proximity. For example, when entering a method or a function, all the executed instructions belong to the same method so they reside very close to each other. The same happens when the program is working on a data record or is analyzing an array. The data items to be addressed belong to the same record or array and thus are relatively close. The PC convention for these memory chunks is a segment, and in general, there are three types of segments with a base register for each one: • Code segment , used for the program’s instructions. The register that holds the code base address is CS (code segment). To reinforce the system’s data integrity, the con-tent of the code segment cannot be accessed (read or written) by other processes, and only the operating system and the MMU can access its content. • Data segment , used for storing the program’s data. The register that holds the data-base address is the DS (data segment). Due to the need of some programs to use very large data address spaces, sometimes the program may have two data segments.

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