Pipeline Hazards

3 Key excerpts on "Pipeline Hazards"

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  eBook - ePub

  Computer Principles and Design in Verilog HDL

  • Yamin Li(Author)
  • 2015(Publication Date)
  • Wiley

    (Publisher)

  Figure 8.7 as a baseline for the design of our pipelined CPU. The branch and jump instructions cannot be executed by the baseline CPU. We will add some circuits to it to make the branch and jump instructions executable later.

  8.2 Pipeline Hazards and Solutions

  Under ideal conditions, the pipelined CPU can execute a useful instruction during every clock cycle. Because of the overlapping execution of multiple instructions, the pipelined CPU may encounter some situations where an instruction cannot be processed or it will not execute correctly. These situations are called hazards.

  There are three types of hazards in a pipelined CPU: structural hazards, control hazards, and data hazards. This section explains these hazards and gives possible solutions to these problems.

  8.2.1 Structural Hazards and Solutions

  Structural hazards occur when two or more instructions attempt to use a hardware component at the same time but the component can serve only one request. An example of structural hazards is the memory access conflict. Suppose that there is only one memory module; the memory data load/store will conflict with IF because IF takes place during every clock cycle.

  As shown in Figure 8.8 , another example of the structural hazards is that, if an integer divider is designed in a low-cost iterative style that may take tens of clock cycles to get the quotient, the successive divide instruction cannot go through the pipeline until the current division is finished.

  Figure 8.8

  Structural hazards caused by an iterative divider

  This integer division operation may cause another structural hazard: there may be two writes to the integer register file in a clock cycle.

  Generally, any lack of sufficient hardware resources that results in pipeline stalls is a structural hazard. Because the current integrated circuit (IC) technology allows makers to fabricate a large number of transistors on a chip, most of the structural hazards can be solved. For example, there are dedicated instruction caches and data caches in modern CPUs. We can also design a register file with two write ports easily, which we will show in Chapter 10

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  eBook - PDF

  Microprocessor Architecture

  From Simple Pipelines to Chip Multiprocessors

  • Jean-Loup Baer(Author)
  • 2009(Publication Date)
  • Cambridge University Press

    (Publisher)

  Even in the absence of exceptional conditions, three forms of hazards can disrupt the functioning of the pipeline. They are: 2.1 Pipelining 35 1. Structural hazards, when stages compete for shared resources or when buffers (e.g., pipeline registers between stages) overflow. In our simple case, we have avoided this form of hazards. 2. Data hazards , when an instruction in the pipeline depends on an instruction that has not yet completed its operation. 3. Control hazards , when the flow of control is not sequential. Data hazards occur because of data dependencies between instructions that are con-currently in the pipeline. More specifically, assume that the execution of instruction i must precede that of instruction j in order to respect the semantics of the program order. We say that instruction j is data-dependent on instruction i if the output of instruction i is an input operand for instruction j . Such a dependency is called a read-after-write , or RAW, dependency. Consider the following example: EXAMPLE 1: i : R7 ← R12 + R15 i + 1: R8 ← R7 − R12 i + 2: R15 ← R8 + R7 There are three RAW dependencies: Instruction i + 1 has a RAW dependency with instruction i , because one of its input registers, register R7, is the output register of instruction i. Instruction i + 2 has a RAW dependency with instruction i , for the same reason. Instruction i + 2 has a RAW dependency with instruction i + 1, because one of its input registers, register R8, is the output register of instruction i + 1. Register R12, which is a common source register for instructions i and i + 1, does not cause any dependency. Another form of dependency, called write-after-read , or WAR, dependency, (or also called anti-dependency) appears in Example 1, in that register R15, an input operand of instruction i , is the output register of instruction i + 2.

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  eBook - ePub

  Computer Architecture

  Fundamentals and Principles of Computer Design, Second Edition

  • Joseph D. Dumas II(Author)
  • 2016(Publication Date)
  • CRC Press

    (Publisher)

  At least that is the way things are supposed to happen under the sequential execution model. Once again, however, if multiple execution units are employed, it is possible that I 2 and I 3 may execute out of their programmed order. If this were to happen, I 2 could mistakenly use the new value in R3 that had been updated by I 3 rather than the old value computed by I 1. This is one more situation, known as an antidependence or WAR hazard, that must be guarded against in a machine in which out-of-order execution is allowed. There is one other possible relationship between instructions that reference the same location for data and might have their execution overlapped in a pipeline(s). This “read after read” situation is the only one that never creates a hazard. In our example, both I 1 and I 3 read R1 for use as a source operand. Because R1 is never modified (written), both instructions are guaranteed to read the correct value regardless of their order of execution. Thus, a simple rule of thumb is that for a data hazard to exist between instructions, at least one of them must modify a commonly used value. 4.3.7 Controlling instruction pipelines Controlling the operation of pipelined processors in order to detect and correct for data hazards is a very important but very complex task, especially in machines with multiple execution units. In a machine with only one pipelined instruction execution unit, RAW hazards are generally the only ones a designer must worry about. (The exception would be in the very unusual case in which more than one stage of the pipeline is capable of writing a result.) Control logic must keep track of (or “reserve”) the destination register or memory location for each instruction in progress and check it against the source operands of subsequent instructions as they enter the pipe

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