Autonomic Networking-on-Chip

Bio-Inspired Specification, Development, and Verification

Phan Cong-Vinh

• Publisher: CRC Press
• Year: 2018
• eBook ISBN: 9781351833714
• Edition: 1
• Topic: Computer Science
• Subtopic: Computer Engineering
• Index: Computer Science

Despite the growing mainstream importance and unique advantages of autonomic networking-on-chip (ANoC) technology, Autonomic Networking-On-Chip: Bio-Inspired Specification, Development, and Verification is among the first books to evaluate research results on formalizing this emerging NoC paradigm, which was inspired by the human nervous system.

The FIRST Book to Assess Research Results, Opportunities, & Trends in "BioChipNets"

The third book in the Embedded Multi-Core Systems series from CRC Press, this is an advanced technical guide and reference composed of contributions from prominent researchers in industry and academia around the world. A response to the critical need for a global information exchange and dialogue, it is written for engineers, scientists, practitioners, and other researchers who have a basic understanding of NoC and are now ready to learn how to specify, develop, and verify ANoC using rigorous approaches.

Offers Expert Insights Into Technical Topics Including:

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• Bio-inspired NoC

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• How to map applications onto ANoC

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• ANoC for FPGAs and structured ASICs

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• Methods to apply formal methods in ANoC development

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• Ways to formalize languages that enable ANoC

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• Methods to validate and verify techniques for ANoC

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• Use of "self-" processes in ANoC (self-organization, configuration, healing, optimization, protection, etc.)

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• Use of calculi for reasoning about context awareness and programming models in ANoC

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With illustrative figures to simplify contents and enhance understanding, this resource contains original, peer-reviewed chapters reporting on new developments and opportunities, emerging trends, and open research problems of interest to both the autonomic computing and network-on-chip communities. Coverage includes state-of-the-art ANoC architectures, protocols, technologies, and applications. This volume thoroughly explores the theory behind ANoC to illustrate strategies that enable readers to use formal ANoC methods yet still make sound judgments and allow for reasonable justifications in practice.

1

A Bio-Inspired Architecture for Autonomic Network-on-Chip

M. Bakhouya

Universite De Technologie De Belfort Montbeliard, Belfort, France

CONTENTS

1.1 Introduction

1.2 Infrastructure level

1.2.1 Topology customization

1.2.2 Bandwidth allocation

1.2.3 Buffer allocation

1.3 Communication level

1.3.1 Switching modes

1.3.2 Routing schemes

1.3.3 Flow control schemes

1.4 Application level

1.5 BNoC Architecture

1.5.1 Immune system principles

1.5.2 BNoC principles

1.5.3 Simulation results

1.6 Conclusions

Network-on-chip has been recently proposed for SoC (System-on-Chip) applications design to achieve better performance and lower energy consumption when compared with conventional on-chip bus architectures. The past few years’ research in the domain of NoC (Network-on-Chip) has been concentrated on application-specific approaches. These approaches are design-time parameterized and do not consider run-time configuration of different NoC parameters, which are hard to predict in early development stages. More precisely, architecture and system parameters, such as routing algorithm, switching scheme and flits’ size, should be adapted at runtime. To address the uncertainty in NoC applications and efficiently use resources, NoC architectures must be adaptive, for example, by rerouting at run time traffic from congested area or by dynamically changing links bandwidth. In this chapter, run-time approaches proposed for autonomic NoCs (ANoCs) are first presented. An approach inspired by the immune system for ANoCs is introduced. The immune system has a useful set of organizing principles, such as self-configuration, self-optimization, and self-healing, that can guide the design of autonomic network-on-chip.

1.1 Introduction

The effectiveness of SoCs is often determined by on-chip interconnect (OCI). SoC applications require the OCI to handle a large amount of traffic by providing low latency communications and high throughput while minimizing the area overhead and energy consumption. The interconnect architectures used in current SoCs to integrate components are based on bus schemes. With the increasing complexity of SoC and its communications requirements, NoC has emerged as the pervasive communication fabric to connect different IP (Intellectual Property) core elements in many-core chips and as a solution of nonscalable shared bus schemes [72, 291]. The main objectives are to satisfy quality of service requirements, to optimize resources’ usage, and to minimize the energy consumption by separating the communication from the computation.

Different NoC based architectures using packet-switching have been studied and adapted recently for SoC design. Examples of these architectures are Fat-Tree (FT), 2D mesh, Ring, Butterfly-Fat Tree (BFT), Torus, Spidergon, Octagon, and WK [237, 290]. These on-chip interconnect architectures draw on concepts inherited from parallel and general computer networks, which are well-established research topics. There are differences between these two systems, despite some issues they have in common. For example, in NoCs, switches are more resource-constrained (e.g., silicon area) than those in general computer networks. Communication links of NoCs are relatively shorter than those in computer networks, allowing tight synchronization between routers. All these difference make the tradeoffs in their design very different [72]. Therefore, NoCs should be scalable and adaptive to support various applications by selecting the most suitable parameters based on the requirements of the current application and system conditions.

Several approaches have been proposed to deal with NoCs design and can be classified into two main categories, design-time approaches and run-time approaches. Design-time approaches are generally tailored an application domain or a specific application by providing an application-specific NoC. All parameters, such as the on-chip interconnect architecture (i.e., topology), routing, and switching schemes, are defined at design time [29, 234]. Run-time approaches, however, provide techniques that allow a NoC to autonomously adapt its structure and its behavior during the course of its operation (i.e., at run time).

Recently, there has been a great deal of interest in the development of run-time approaches for autonomic NoC. These approaches can be classified, as illustrated in Figure 1.1, based on the level in which the adaptation is carried out, at the application level, at the communication level, or at the architecture level. In this chapter, a state of the art review of run-time approaches proposed in the literature for ANoCs with adaptive capabilities are presented. Adaptive capabilities have been seen in natural and biological systems and have inspired many researches to develop adaptive systems. In other words, biological and natural systems have been exploited in a variety of computation systems and been perceived as an efficient system model for developing adaptive systems [10, 102, 204] and reconfigurable and evolvable hardware systems [112, 270, 295, 303].

After describing run-time approaches, a bio-inspired architecture, called BNoC, inspired by biological immune system (BIS) is introduced for autonomic NOCs. Biological immune system could allow the design of autonomic NoCs with promising adaptive capabilities. The objective is to implement these capabilities within the system to adapt to environment changes and the dynamic of its computing elements. BNoC could react like an immune system against pathogens that have entered the body. It detects the infection (i.e., applications behavior or system state changes) and delivers a response to eliminate it (i.e., adapt to changes). The aim is to highlight how biological immune system principles can be incorporated into the design of autonomic middleware for NoCs.

FIGURE 1.1
Classification of run-time approaches for ANoCs.

The rest of this chapter is organized as follows. In section 2, we present run-time approaches proposed for adapting the application to the NoC architecture. Section 3 presents approaches dealing with the adaptation at the communication level. In section 4, we present approaches proposed mainly to optimize some architecture parameters. In section 5, approaches dealing with mapping and scheduling issues at the application level are presented. A bio-inspired approach is introduced and some preliminary results are presented in section 6. Conclusions and future work are given in section 7.

1.2 Infrastructure level

At the infrastructure layer, the performance and the efficiency of the NoC are highly dependent on the on-chip interconnect. Switches constitute the active component that influences on latency and throughput. For example, designing efficient switches with minimum buffer size (a critical resource) represents a main issue for the success of NoC design. Links are components that transport data between switches, efficient allocation of their capacity, decreasing their length or increasing their number may increase the performance of SoC applications. Hence, on-chip interconnect configuration, bandwidth allocation, and buffer minimization are three main issues that should be addressed when designing ANoC. The rest of this section describes approaches mainly proposed to address these issues.

1.2.1 Topology customization

Many studies have shown that to improve the performance of specific application domain the NoC architecture must be customized by inserting additional links between switches. More precisely, on-chip interconnect architecture can be designed and customized for a priori known set of computing resources (IP cores), and given pre-characterized traffic patterns among them [39]. These approaches can be classified into two main classes: synthesizing approaches and customizing approaches. The first class concerns techniques proposed to fully customize the architecture that is more suitable for a particular application and does not necessarily conform to regular topologies (e.g., 2D mesh). These techniques, such as presented in [221, 246, 284], despite their capabilities to maximize the performance by offering techniques for incorporating synthesized on-chip interconnect architectures that are more suitable for a given application, they suffer from providing architectures with high regularity in reasonable time [194]. Customizing approaches, however, focus mainly to start with a regular on-chip interconnect architecture like 2D mesh and partially customize it by inserting long-range links. For example, an algorithm for customizing a standard mesh NoC by inserting few application-specific long-range links was proposed in [234, 289].

These approaches are mainly proposed to customize/synthesize, at design time, on-chip interconnects given an application traffic workload. They deal with the selection of an on-chip interconnect architecture to accommodate the expected application-specific data traffic patterns during design space exploration phase. For autonomic NoC, in which traffic pattern is not known or predictable in advance, runtime approaches are required.

Recently, approaches to dynamically reconfigure the on-chip interconnect by establishing at runtime links are proposed. For example, a power-aware network approach has been proposed in [280]. This approach responds to the bursts and dips in traffic by turning links “on” and “off” at runtime. However, this approach is based on the assumption that the future traffic patterns are predictable based on the observation of the past traffic.

In [308], an approach is proposed to dynamically establish interconnections by adapting the physical network. Similar to circuit-switching techniques, connections are set when needed and released when the data exchange is finished. Experiments results are reported to show the viability of this approach, but it does not scale well as the number of required links increases...

Table of contents

• Cover
• Half Title
• Title Page
• Copyright Page
• Table of Contents
• List of Figures
• List of Tables
• Foreword
• Preface
• About the Editor
• List of Contributors
• 1 A Bio-Inspired Architecture for Autonomic Network-on-Chip
• 2 Bio-Inspired NoC Architecture Optimization
• 3 An Autonomic NoC Architecture Using Heuristic Technique for Virtual-Channel Sharing
• 4 Evolutionary Design of Collective Communications on Wormhole NoCs
• 5 Formal Aspects of Parallel Processing on Bio-Inspired on-Chip Networks
• 6 HAMSoC: A Monitoring-Centric Design Approach for Adaptive Parallel Computing
• 7 Toward Self-Placing Applications on 2D and 3D NoCs
• 8 Self-Adaption in SoCs
• Bibliography
• Index