Low-Power Processors and Systems on Chips

Christian Piguet

• Publisher: CRC Press
• Year: 2018
• eBook ISBN: 9781351836470
• Edition: 1
• Topic: Tecnologia e ingegneria
• Subtopic: Ingegneria elettronica e telecomunicazioni

The power consumption of microprocessors is one of the most important challenges of high-performance chips and portable devices. In chapters drawn from Piguet's recently published Low-Power Electronics Design, this volume addresses the design of low-power microprocessors in deep submicron technologies. It provides a focused reference for specialists involved in systems-on-chips, from low-power microprocessors to DSP cores, reconfigurable processors, memories, ad-hoc networks, and embedded software.Low-Power Processors and Systems on Chips is organized into three broad sections for convenient access. The first section examines the design of digital signal processors for embedded applications and techniques for reducing dynamic and static power at the electrical and system levels. The second part describes several aspects of low-power systems on chips, including hardware and embedded software aspects, efficient data storage, networks-on-chips, and applications such as routing strategies in wireless RF sensing and actuating devices. The final section discusses embedded software issues, including details on compilers, retargetable compilers, and coverification tools.Providing detailed examinations contributed by leading experts, Low-Power Processors and Systems on Chips supplies authoritative information on how to maintain high performance while lowering power consumption in modern processors and SoCs. It is a must-read for anyone designing modern computers or embedded systems.

I

Low-Power Processors and Memories

1 Techniques for Power and Process Variation Minimization

Lawrence T. Clark and Vivek De

2 Low-Power DSPs

Ingrid Verbauwhede

3 Energy-Efficient Reconfigurable Processors

Raphaël David, Sébastien Pillement, and Olivier Sentieys

4 Macgic, a Low-Power Reconfigurable DSP

Flavio Rampogna, Pierre-David Pfister, Claude Arm, Patrick Volet, Jean-Marc Masgonty, and Christian Piguet

5 Low-Power Asynchronous Processors

Kamel Slimani, Joao Fragoso, Mohammed Es Sahliene, Laurent Fesquet, and Marc Renaudin

6 Low-Power Baseband Processors for Communications

Dake Liu and Eric Tell

7 Stand-By Power Reduction for SRAM Memories

Stefan Cserveny, Jean-Marc Masgonty, and Christian Piguet

8 Low-Power Cache Design

Vasily G. Moshnyaga and Koji Inoue

9 Memory Organization for Low-Energy Embedded Systems

Alberto Macii

1

Techniques for Power and Process Variation Minimization

Lawrence T. Clark

Arizona State University

Vivek De

Intel Labs

1.1 Introduction

1.2 Integrated Circuit Power

Active Power and Delay • Leakage Power

1.3 Process Selection and Rationale

Effective Frequency

1.4 Leakage Control via Reverse Body Bias

RBB on a 0.18-μM IC • Circuit Configuration • Layout • Regulator Design • Limits of Operation • Measured Results

1.5 System Level Performance

System Measurement Results

1.6 Process, Voltage, and Temperature Variations

Process Variation • Supply Voltage Variation • Temperature Variation

1.7 Variation Impact on Circuits and Microarchitecture

Design Choice Impact • Microarchitecture Choice Impact

1.8 Adaptive Techniques and Variation Tolerance

Body Bias Control Techniques • Adaptive Body Bias and Supply Bias

1.9 Dynamic Voltage Scaling

Clock Generation • Experimental Results

1.10 Conclusions

References

1.1 Introduction

For more than a decade, integrated circuit (IC) power has been steadily increasing due to higher integration and performance enabled by process scaling. As shrinking transistor dimensions are fabricated, and as the absolute value of the dimensions diminish, greater device variations must be addressed. Until recently, increased power was driven primarily by active switching power. Threshold voltages must be decreased to maintain performance at the lower supply voltages required by thinner oxides, however, raising drain to source leakage exponentially. Steeper doping gradients and higher electric fields increase other leakage components, giving rise in sub-0.25-μm generations to DC leakage currents that may limit overall power and performance in future chips. This comes on top of still increasing active power dissipation, driven by architectural changes such as greater parallelism and deeper pipelining. The latter implies fewer gates per stage and, in turn, requires more aggressive circuit techniques such as domino, which can also increase active power. Having fewer logic stages increases the susceptibility to process variations. Finally, as scaling requires lower voltages, in-die and system-level voltage variations are also increasingly problematic.

The focus of this chapter includes the design implications of increasing device variation and leakage. The mechanisms are a direct result of basic physics and will continue to grow in importance over time, requiring design effort to mitigate them. Variation in microprocessor frequency has been dealt with by “speed binning,” whereby faster dies are separated and sold at a premium. Dies with inadequate speed or excessive standby current are discarded. These yield considerations are important for robust design. We also discuss design techniques, notably the application of body bias and supply voltage adjustment, which can help deal with both variation and average leakage, as well as active power. Examples from fabricated designs demonstrating the efficacy of the techniques are discussed.

1.2 Integrated Circuit Power

Increasing leakage currents are a natural by-product of transistor scaling and comprise a significant portion of the total power since the 0.25-μm-process generation. By the 90-nm technology node, it can contribute over a fifth of the total IC power on high-performance products [1]. The profusion of battery-powered “hand-held” devices introduced in recent years (e.g., cell phones and personal digital assistants) has made power management a first-order design consideration. These sections focus on circuit design approaches to alleviate leakage power using reverse body bias (RBB) “Drowsy” mode when an IC is in a standby mode and later, in Section 18.9, optimizing the active power by dynamic voltage management (DVM). Although other implementations are briefly discussed, the bulk of the discussion describes the specific implementation on the 0.18-μm XScale microprocessor cores intended for system-on-chip (SoC) applications [2].

1.2.1 Active Power and Delay

The total power of a static CMOS integrated circuit is given by

${\text{P}}_{\text{tot}}{\text{= P}}_{\text{dyn}}{\text{+ P}}_{\text{static}}{\text{+ P}}_{\text{short-circuit}}$

(1.1)

representing the dynamic power (i.e., that due to charging and discharging capacitances during switching) the static leakage power, and the “short-circuit” or crowbar power due to both P and N transistors being on simultaneously during a switching event, respectively. The latter term tracks with the active power and is generally on the order of 5% or less for well-designed circuits. It is typically ignored, as it will be here. The dynamic power of a digital circuit follows the well-known

${\text{P}}_{\text{dyn}}=a/2\text{C}{\text{V}}_{d{d}^2}\text{F}$

(1.2)

where C is the switched capacitance, V_dd is the power supply voltage, F is the operating frequency, and a is the switching activity factor measured in transitions per clock cycle. Leveraging the V_dd² dependency is consequently the most effective method for lowering digital system power; however, the switching speed of a digital circuit with a fixed input slope and fixed load is given by Chen and Hu [3]:

${\text{T}}_{\text{delay}}{\text{=KV}}_{\text{dd}}{\text{/(V}}_{\text{dd}}{\text{–}\text{V}}_{\text{t}}{\text{)}}^{\text{α}}$

(1.3)

where α^⋆ is typically 1.1 to 1.5 for modern velocity saturated devices, tending toward the former for NMOS and the latter for PMOS [4], and K is a constant depending on the process. To first order, this delay dependency on voltage can be treated as linear. The concept of DVM is to limit the V_dd and frequency such that the application latency constraints are met, but the energy to perform the application function is minimized by following the square law dependency of Equation 1.2 instead of linearly tracking F. The chosen frequency F, representing the reciprocal of the worst-case path delay, is constrained by Equation 1.3 for a given supply voltage.

1.2.2 Leakage Power

Leakage power sources are numerous [5], with the primary contributor historically being transistor off state drain to source leakage (I_off). For modern processes having gate dielectric thicknesses under 3 nm, gate leakage I_gate is becoming a larger contributor but is generally smaller than I_off, particularly at high temperatures, given the stronger temperature dependency of $8-12\times /{100}^{°}\text{C}$ for I_off vs. approximately 2×/100°C for I_gate. I_off increases on scaled transistors because, to maintain performance, V_t must be lowered to compensate for decrease in V_dd . This increases the leakage according to

$\text{I}{}_{Off}\propto e^{-V_t/(S/In10)}$

(1.4)

where S is the subthreshold swing given by

$\text{S}\text{=}\frac{KT(In10)}{q}\left(1+\frac{{}^{C}D}{{}^{C}OX}\right)$

(1.5)

where k is the Boltzmann constant, T is the temperature in Kelvin, q is the elementary charge, C_D is the depletion layer capacitance, and C_OX is the gate oxide capacitance. Noting that C_D is nonvanishing, the subthreshold swing parameter S is essentially a fixed parameter for Si MOSFETs, typically 80-100 mV/ decade depending upon the process at room temperature. Referring to Equation 1.4, it is obvious that lowering V_t affects the I_off exponentially.

For gate oxide thicknesses below 3 nm, quantum mechanical (direct band-to-band) tunneling current becomes significant. This leakage is extremely voltage dependent, increasing approximately with V³ [6]. It also increases dramatically with decreasing thickness (e.g., increasing 10× for a change from 2.2 nm to 2.0 nm [7]). Gate-induced drain leakage (GIDL) at the gate-drain edge is important at low current levels and high applied voltages. It is most prevalent in the NMOS transistors where it is about two orders of magnitude greater than for PMOS devices. For a gate having a 0-V bias with the drain at V_dd, significant band bending occurs in the drain region, allowing electron-hole pair creation. Essentially, the gate voltage attempts to invert the drain region, but because the holes are rapidly swept out, a deep depletion condition occurs [8]. The onset of this mechanism can be lessened by limiting the drain to gate voltage. It can be exacerbated by high source or drain to body voltages. Diode area leakage components from both the source-drain diodes and the well diodes are generally negligible with respect to I_off and GIDL components. This is also improved by compensation implants...

Table of contents

• Cover
• Half Title
• Title Page
• Copyright Page
• Table of Contents
• I Low-Power Processors and Memories
• II Low-Power Systems on Chips
• III Embedded Software
• Index