Network-on-Chip

The Next Generation of System-on-Chip Integration

Santanu Kundu, Santanu Chattopadhyay

• Publisher: CRC Press
• Year: 2018
• ISBN:
  9781351831963
• Edition: 1
• Topic: Technologie et ingénierie
• Subtopic: Microélectronique

Addresses the Challenges Associated with System-on-Chip Integration

Network-on-Chip: The Next Generation of System-on-Chip Integration

examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends.

Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design.

This text comprises 12 chapters and covers:

• The evolution of NoC from SoC—its research and developmental challenges
• NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces
• The router design strategies followed in NoCs
• The evaluation mechanism of NoC architectures
• The application mapping strategies followed in NoCs
• Low-power design techniques specifically followed in NoCs
• The signal integrity and reliability issues of NoC
• The details of NoC testing strategies reported so far
• The problem of synthesizing application-specific NoCs
• Reconfigurable NoC design issues
• Direction of future research and development in the field of NoC

Network-on-Chip: The Next Generation of System-on-Chip Integration

covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems.

1

Introduction

1.1 System-on-Chip Integration and Its Challenges

Continuous reduction in time to market, required by the multimedia and consumer electronics commodities, makes full-custom design inappropriate. It has led to the design based on reuse of intellectual property (IP) cores. With the growing complexity in consumer-embedded products, a single-chip implementation integrating numerous IP cores performing various functions and possibly operating at different clock frequencies is now a well-established one. Such an implementation is conveniently known as system-on-chip (SoC). Depending on application domains and versatility, SoC can be classified into two categories: (1) general-purpose multiprocessor SoC (MPSoC) and (2) application-specific SoC.

Improving the performance and efficiency of a traditional large uniprocessor architecture is no longer achievable, thus enhancing the demand for parallel processing. This, in turn, has resulted in a revolution in microprocessor architecture—chip multiprocessing (CMP) system. For boosting up the performance of CMP-based systems, researchers have adopted SoC platform to build a general-purpose MPSoC for supporting a wide range of applications. This type of SoC is categorized by having a homogeneous set of processing elements and storage arrays. Application-specific SoC, as the name suggests, is dedicated to a specific application. This type of SoC, in many cases, contains heterogeneous processing elements (e.g., processors, controllers, and digital signal processors) and a number of domain-specific hardware accelerators. This heterogeneity may lead to a specific traffic pattern requirement. Hence, a prior knowledge of traffic pattern is required when the system is designed.

Shared medium arbitrated bus is the commonly used communication backbone in modern SoCs. Although this architecture has the advantages of simple topology, extensibility, and low area cost, a shared bus allows only one communication at a time that may block all other buses in the hierarchy. Thus, bus-based SoC does not scale the system performance with the number of cores attached. Its bandwidth is also shared by all the cores (Grecu et al. 2004). Usage of segmented bus architecture where a shared bus is segmented to multiple buses using bridges also suffers from the same problem of bandwidth sharing. There is also a problem of distributing a synchronous clock signal over the whole chip. In deep submicron (DSM) technologies, according to the International Technology Roadmap for Semiconductors (ITRS) report (ITRS 2001), the delay of local wires and logic gates reduces with every process generation, whereas global wire delay increases exponentially, or at best linearly, by inserting repeaters as shown in Figure 1.1. For a relatively long bus, this delay is significant due to its high intrinsic parasitic resistance and capacitance. As the IP blocks are connected to the bus, they will add more capacitance to it, which may enhance the delay. In ultra-DSM processes, it has been observed that long wires mostly fall in the critical path of the design (Sylvester and Keutzer 2000; Kapur et al. 2002). The long wires in DSM regime also introduce many signal integrity problems, such as crosstalk noise, crosstalk delay, IR drop, and electromagnetic interference (EMI). Moreover, the power consumption of the global wires along with their drivers and repeaters can be a significant portion of the overall SoC power budget. Therefore, in DSM technologies, on-chip communication efficiency has become one of the key factors determining the overall system performance and cost. The major challenge, SoC researchers face today, is to come up with structured, scalable, reusable, and high-performance interconnection architectures.

FIGURE 1.1
Projected relative delay for local and global wires and for logic gates at different technologies. (Data from ITRS, International technology roadmap for semiconductors, Technical report, International Technology Roadmap for Semiconductors, 2001.)

1.2 SoC to Network-on-Chip: A Paradigm Shift

Several research groups from academia and industry have started to find out the communication backbone of next-generation many-core-based SoCs for supporting the new inter-core communication demands. Point-to-point dedicated links can be a good alternative to global bus for a limited number of cores in a SoC in terms of bandwidth, latency, and power consumption. However, the number of links needed increases exponentially as the number of cores increases. Thus, for a large system, it may create a routing problem (Bjerregaard and Mahadevan 2006). A centralized crossbar switch overcomes some of the limitations of the buses. Again, connecting large number of cores to a single switch is not very effective as it is not ultimately scalable and, thus, is an intermediate solution only (Bjerregaard and Mahadevan 2006). At the system level, up to a certain number of cores on a single chip, the performance of traditional bus-based SoCs are expected to be satisfactory. But in a many-core regime, as the number of cores residing on a SoC increases significantly, it has a profound effect in shifting the focus from computation to communication.

To overcome the above-mentioned problems, several research groups have started to investigate systematic platform-based approaches to design the communication backbone of MPSoC. On-chip interconnection network is one solution to integrate IPs in complex SoCs. Network-on-chip (NoC) has emerged as the viable alternative for the design of modular and scalable communication architectures. The IP cores communicate with each other via the router-based network. A core is attached to a router through a network interface (NI) module (Benini and Micheli 2002). The network is used for packet-switched on-chip communication among routers, whereas the NIs enable seamless communication between various cores and the network. The need for global synchronization can thus disappear. NoC supports the globally asynchronous locally synchronous (GALS) style for multicore communication in SoCs.

The concept of on-chip network has been borrowed from off-chip interconnection networks where a single router is implemented per chip (Gratz et al. 2006). The bandwidth of off-chip networks is typically lower than that of on-chip networks. Off-chip networks are constrained by bit width, as each extra bit incurs one more pin. Also, the off-chip routers need to be connected by explicit board traces. This affects the overall system latency and aggravates the synchronization problem (Jerger and Peh 2009).

The introduction of on-chip networks in SoC design is an evolution of bus interconnect technology. Figure 1.2 shows a NoC structure where heterogeneous IP cores (CPU, DSP, etc.) communicate with each other via a network and NI modules. The function of NI is to isolate the computation from communication. The network consists of switches (routers) and point-to-point communication links between them. Routers route the packets from the source node to the destination node depending on the underlying network topology and routing strategy. The length of the point-to-point links should be small to reduce wire delay.

FIGURE 1.2
The NoC paradigm. (Data from Angiolini, F., NoC Architectures, n.d., http://www-micrel.deis.unibo.it/MPHS/slidecorso0607/nocsynth.pdf.)

To mitigate the ever increasing design productivity gap and to meet the time-to-market requirement, reuse of IP cores is widely used in SoC development. Besides IP cores, the bus interface protocol can also be reused to integrate the IPs. While reuse is one of the key challenges that IC design houses try to address, reuse of IPs, NI, and communication infrastructure such as routers, underlying network, and flow control protocols can be adopted in the NoC paradigm. Although selection of network topology and router architecture is purely application specific, reusing these in different applications will not give the optimal solution. Hence, the reusability is limited to a particular type of applications. For example, the network topology and router architecture used for mobile application cannot be same as those of video processing application. For similar applications, the design and verification effort due to reuse will be drastically reduced.

NoC is a specific flavor of interconnection networks and involves several abstraction layers such as physical, data link, network, and transport layers (Jantsch and Tenhunen 2003), which are described as follows:

• The physical layer determines the number and length of wires connecting resources and switches.

• The data link layer defines the protocol of communication between a resource and a switch, and between the two switches. Both the physical and data link layers are dependent on the technology. Thus, for each new technology, these layers are defined.

• The network layer defines how a packet is transmitted over the network from an arbitrary sender to an arbitrary receiver directed by the receiver’s network address. This layer is also technology dependent.

• The transport layer is technology independent. In this layer, message size can be variable. This layer breaks the message into network layer packets.

Interconnection networks have been studied for more than the past two decades and a solid foundation of design techniques has been described in several text books (Duato et al. 2003; Dally and Towles 2004). With increasing communication demand, the introduction of interconnection network in SoC design has paved the route to NoC research almost a decade ago. Mullins (2009) has listed more than 400 related articles addressing all these aspects. NoC is today becoming an emerging research topic including hardware communication infrastructure, software and operating system services, CAD tools for NoC synthesis, and so on.

1.3 Research Issues in NoC Development

The major research problems in NoC design can be broadly classified into four different dimensions—communication infrastructure, communication paradigm, evaluation framework, and application mapping—as addressed in the works of Ogras et al. (2005) and Marculescu et al. (2009). This section first highlights these issues briefly followed by other associated issues.

The first dimension of research is focused on choice of communication infrastructure. The communication infrastructure design essentially points to the design of underlying hardware acting as the backbone for the on-chip communication network. Selection of network topology, design of router architecture with proper buffer organization, determining inter-router link width, clocking strategies, floorplanning, and layout design are the key design aspects of this dimension. The routers are often connected in certain topologies whose performance behaviors are well known to the distributed system design community and suit well for on-chip realizations. Individual routers are designed using some specific switching techniques, such as wormhole and virtual cut-through. Flow control is performed via handshaking signals between adjacent routers. The router’s buffer space minimization and simplified buffer control mechanisms are two important features of the NoC design, as they directly affect the overall area–power overheads and network latency. To solve the problem of clock skew, the individual cores and routers are allowed to operate at their own clocks, giving rise to a GALS scheme. Another important hardware aspect in designing a complete NoC is the integration of cores with the routers. This needs the design of NI modules between the two.

The second dimension of research deals with the communication paradigm on a given NoC platform. Once the infrastructure has been finalized, the next important task is to design the communication methodology between the cores via the established network. Routing policies, switching techniques, congestion control, power and thermal management, and fault tolerance and reliability issues are the main focus of this set. It, first of all, necessitates the fixing of routing strategy. This is one of the very rich areas of research in NoC design. It has profound effect on the performance of the NoC as this chiefly determines the number of hops to be traversed in each communication, congestion, traffic load distribution in different routers, and so on. The domain is often complicated by the requirement to support the quality-of-service (QoS). Arbitration of network resources in terms of FIFOs and channels between the contending simultaneous communications is essential to ...