
Reconfigurable and Adaptive Computing
Theory and Applications
- 222 pages
- English
- PDF
- Available on iOS & Android
Reconfigurable and Adaptive Computing
Theory and Applications
About this book
Reconfigurable computing techniques and adaptive systems are some of the most promising architectures for microprocessors. Reconfigurable and Adaptive Computing: Theory and Applications explores the latest research activities on hardware architecture for reconfigurable and adaptive computing systems.
The first section of the book covers reconfigurable systems. The book presents a software and hardware codesign flow for coarse-grained systems-on-chip, a video watermarking algorithm for the H.264 standard, a solution for regular expressions matching systems, and a novel field programmable gate array (FPGA)-based acceleration solution with MapReduce framework on multiple hardware accelerators.
The second section discusses network-on-chip, including an implementation of a multiprocessor system-on-chip platform with shared memory access, end-to-end quality-of-service metrics modeling based on a multi-application environment in network-on-chip, and a 3D ant colony routing (3D-ACR) for network-on-chip with three different 3D topologies.
The final section addresses the methodology of system codesign. The book introduces a new softwareâhardware codesign flow for embedded systems that models both processors and intellectual property cores as services. It also proposes an efficient algorithm for dependent task softwareâhardware codesign with the greedy partitioning and insert scheduling method (GPISM) by task graph.
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Information
Table of contents
- Front Cover
- Contents
- List of Figures
- List of Tables
- Preface
- Editors
- Contributors
- Chapter 1: Effective and Efficient Design Space Exploration for Heterogeneous Microprocessor Systems-on-Chip
- Chapter 2: Integer DCT-Based Real-Time Video Watermarking for H.264 Encoder
- Chapter 3: FPGA-Accelerated Algorithm for the Regular Expressions Matching System
- Chapter 4: Case Study of Genome Sequencing on an FPGA : Survey and a New Perspective
- Chapter 5: Interprocess Communication via Crossbar for Shared Memory Multiprocessor Systems-on-Chip
- Chapter 6: Extended Quality of Service Modeling Based on Multiapplication Environment in Network-on-Chip
- Chapter 7: Ant Colony Routing for Latency Reduction in 3D Networks-on-Chip
- Chapter 8: Codem : Software/Hardware Codesign for Embedded Multicore Systems Supporting Hardware Services
- Chapter 9: Greedy Partitioning and Insert Scheduling Algorithm for HardwareâSoftware Codesign on MPSoCs
- Back Cover