Digital Design and Fabrication

Vojin G. Oklobdzija

• Publisher: CRC Press
• Year: 2017
• Print ISBN: 9780849386022
• eBook ISBN: 9781351838115
• Topic: Computer Science
• Subtopic: Computer Engineering
• Index: Computer Science

In response to tremendous growth and new technologies in the semiconductor industry, this volume is organized into five, information-rich sections. Digital Design and Fabrication surveys the latest advances in computer architecture and design as well as the technologies used to manufacture and test them. Featuring contributions from leading experts, the book also includes a new section on memory and storage in addition to a new chapter on nonvolatile memory technologies.

Developing advanced concepts, this sharply focused book—

• Describes new technologies that have become driving factors for the electronic industry
• Includes new information on semiconductor memory circuits, whose development best illustrates the phenomenal progress encountered by the fabrication and technology sector
• Contains a section dedicated to issues related to system power consumption
• Describes reliability and testability of computer systems
• Pinpoints trends and state-of-the-art advances in fabrication and CMOS technologies
• Describes performance evaluation measures, which are the bottom line from the user's point of view
• Discusses design techniques used to create modern computer systems, including high-speed computer arithmetic and high-frequency design, timing and clocking, and PLL and DLL design

IV

Design for Low Power

1. 12 Design for Low Power Hai Li, Rakesh Patet Kinyip Sit, Zhenyu Tang, and Shahram Jamshidi
   1. Introduction • RTL and Gate Level Dynamic Power Optimization • Power Optimizations in Transistor Level for Static and Dynamic Circuits • Power Reduction at Physical Implementation Level • CAD Tools for Auto Power Optimization • Conclusion
2. 13 Low-Power Circuit Technologies Masayuki Miyazllki
   1. Introduction • Basic Theories of CMOS Circuits • Supply Voltage Management • Threshold Voltage Management • Clock Distribution Management
3. 14 Techniques for Leakage Power Reduction Vivek De, Ali Keshavarzi, Siva Narendra, Dinesh Somasekhar, Shekhar Borkar, James Kao, Raj Nair, and Yibin Ye
   1. Introduction • Transistor Leakage Current Components • Circuit Subthreshold Leakage Current • Leakage Control Techniques
4. 15 Dynamic Voltage Scaling Thomas D. Burd
   1. Introduction • Processor Operation • Dynamically Varying Voltage • A Custom DVS Processor System • Design Issues • Conclusions
5. 16 Lightweight Embedded Systems Foad Dabiri, Tammara Massey, Ani Nahapetian, Majid Sarrafzadeh, and Roozbeh Jafari
   1. Introduction • Online Dynamic Voltage Scaling for Discrete Voltages • Reliable and Fault Tolerant Networked Embedded Systems • Security in Lightweight Embedded Systems • Conclusion
6. 17 Low-Power Design of Systems on Chip Christian Piguet
   1. Introduction • Power Reduction from High to Low Level • Large Power Reduction at High Level • Low-Power Microcontroller Cores • Low-Power DSP Embedded in SoCs • Low-Power SRAM Memories • Low-Power Standard Cell Libraries • Leakage Reduction at Architectural Level
7. 18 Implementation-Level Impact on Low-Power Design Katsunori Seno
   1. Introduction • System Level Impact • Algorithm Level Impact • Architecture Level Impact • Circuit Level Impact • Process/Device Level Impact • Summary
8. 19 Accurate Power Estimation of Combinational CMOS Digital Circuits Hendrawan Soeleman and Kaushik Roy
   1. Introduction • Power Consumption • Probabilistic Technique to Estimate Switching Activity • Statistical Technique • Experimental Results • Summary and Conclusion
9. 20 Clock-Powered CMOS for Energy-Efficient Computing Nestoras Tzartzanis and William Athas
   1. Introduction • Overview of Clock-Powered Logic • Clock Driver • Energy-Recovery Latch • Interfacing Clock-Powered Signals with CMOS Logic • Driver Comparison • Clock-Powered Microprocessor Design • Conclusions

12
Design for Low Power

Hai Li
Rakesh Patel
Kinyip Sit
Zhenyu Tang
Shahram Jamshidi

Intel Corporation

1. 12.1 Introduction
2. 12.2 RTL and Gate Level Dynamic Power Optimization
   1. Clock Gating • Switching Activity Reduction through Data Gating • Low-Power Logic Synthesis and FSM Optimization • Bus Encoding
3. 12.3 Power Optimizations in Transistor Level for Static and Dynamic Circuits
   1. Static Circuit Design Considerations • Dynamic Circuit Design Considerations • Power Consumption due to Contention • Power-Delay Product Comparison
4. 12.4 Power Reduction at Physical Implementation Level
   1. Power Reduction Techniques in Floor Plan • Interconnect Power Reduction Techniques
5. 12.5 CAD Tools for Auto Power Optimization
   1. Power Analysis at Different Levels of Abstraction • CAD Tools for Clock Gating, Cell Sizing, and Transistor Sizing • CAD Tools for Low-Power Clock Tree Synthesis and Voltage Island • CAD Tools for Multiple Threshold Voltage and Multiple Channel Length Devices
6. 12.6 Conclusion

12.1 Introduction

In every process generation, as transistor size decreases it enables to pack more features on silicon. Moore's law predicts doubling of transistors every 18 months. From switching power perspective, it means doubling power consumption every 18 months if device geometry is not reduced. As we migrate to smaller device geometry, transistor capacitance and threshold voltage are reduced thus allowing for a lower supply voltage operation. The benefits of lower capacitance as well as lowering of supply voltage will not offset the increase in power due to added features on the silicon and higher frequency of operation. From one process generation to the next, variety of design techniques are implemented to ensure power consumption stays relatively constant. As shown in Figure 12.1, since the advent of 130 nm technology, switching power consumption from one process generation to the next has remained relatively constant [1].

One of the key design parameters for consideration in any very large scale integration (VLSI) design is average power consumption. The average power is defined as [2,3]

Pavg=Pdynamic+Pstatic (12.1)

FIGURE 12.1 Power trend with technology scaling. (From Hillman, D., Virtual Silicon, and J. Wei, Tensilica, SNUG Implementing Power Management IP for Dynamic and Static Power Reduction in Configurable Microprocessors using the Galaxy Design Platform at 130 nm” SNUG, Boston, MA, 2004. With permission.)

The P_dynamic component comprises power consumption due to transistor switching and P_static component comprises power consumption due to transistor leakage when it is idle. In this chapter, we examine sources of dynamic power consumption and different methods of its reduction in submicron design practices. The P_dynamic has two components, P_switching and P_{short-circuit}. The P_switching is power consumed when transistor is switching and P_{short-circuit} is power consumed due to direct current path between the supply and ground when gate output is switching.

P_{short-circuit} is defined as

Pshort-circuit=λf(VDD−2Vth)3 (12.2)

where

1. λ is a constant
2. V_th is the threshold voltage

Short-circuit power is a small portion of the total P_avg described in Equation 12.2 [2]. For a high-performance ASIC designs, it comprises 10%–20% of total power consumpti...

Table of contents

• Cover Page
• Title Page
• Copyright Page
• Table of Contents
• Acknowledgments
• Preface
• Editor
• Editorial Board
• SECTION I Fabrication and Technology
• SECTION II Memory and Storage
• SECTION III Design Techniques
• SECTION IV Design for Low Power
• SECTION V Testing and Design for Testability
• Index