Sequential Logic and Verilog HDL Fundamentals

Joseph Cavanagh

• Publisher: CRC Press
• Year: 2017
• Print ISBN: 9781498738224
• eBook ISBN: 9781351830027
• Topic: Computer Science
• Subtopic: Computer Engineering
• Index: Computer Science

Sequential Logic and Verilog HDL Fundamentals discusses the analysis and synthesis of synchronous and asynchronous sequential machines. These machines are implemented using Verilog Hardware Description Language (HDL), in accordance with the Institute of Electrical and Electronics Engineers (IEEE) Standard: 1364-1995.

The book concentrates on sequential logic design with a focus on the design of various Verilog HDL projects. Emphasis is placed on structured and rigorous design principles that can be applied to practical applications. Each step of the analysis and synthesis procedures is clearly delineated. Each method that is presented is expounded in sufficient detail with accompanying examples. Many analysis and synthesis examples use mixed-logic symbols incorporating both positive- and negative-input logic gates for NAND (not AND) and NOR (not OR) logic, while other examples utilize only positive-input logic gates. The use of mixed logic parallels the use of these symbols in the industry.

The book is intended to be a tutorial, and as such, is comprehensive and self-contained. All designs are carried through to completion—nothing is left unfinished or partially designed. Each chapter contains numerous problems of varying complexity to be designed by the reader using Verilog HDL design techniques. The Verilog HDL designs include the design module, the test bench module that tests the design for correct functionality, the outputs obtained from the test bench, and the waveforms obtained from the test bench.

Sequential Logic and Verilog HDL Fundamentals presents Verilog HDL with numerous design examples to help the reader thoroughly understand this popular hardware description language. The book is designed for practicing electrical engineers, computer engineers, and computer scientists; for graduate students in electrical engineering, computer engineering, and computer science; and for senior-level undergraduate students.

1.1 Built-In Primitives

1.2 User-Defined Primitives

1.3 Dataflow Modeling

1.4 Behavioral Modeling

1.5 Structural Modeling

1.6 Problems

1

Introduction to Verilog HDL

This chapter provides an introduction to the design methodologies and modeling constructs of the Verilog hardware description language (HDL). Modules, ports, and test benches will be presented. This chapter introduces Verilog in conjunction with combinational logic only.

A module is the basic unit of design in Verilog that describes the Verilog hardware and consists of the following types of modules: built-in logic primitives, user-defined logic primitives, dataflow modeling, behavioral modeling, and structural modeling. A module describes the functional operation of some logical entity and can be a standalone module or a collection of modules that are instantiated into a structural module. Instantiation means to use one or more lower-level modules in the construction of a higher-level structural module. A module can be a logic gate, an adder, a multiplexer, a counter, or some other logical function. Examples will be shown for each type of modeling.

Ports allow the modules to communicate with the external environment; that is, other modules and input/output signals. Ports, also referred to as terminals, can be declared as input, output, or inout. A port is a net by default; however, it can be declared explicitly as a net. A module contains an optional list of ports, as shown below for a full adder. Ports a, b, and cin are input ports; ports sum and cout are output ports.

module full_adder (a, b, cin, sum, cout);

Test benches will also be described. Test benches are used to apply input vectors to the design module in order to test the functional operation of the module in a simulation environment. The test bench for the full adder contains no ports as shown below because it does not communicate with the external environment.

module full_adder_tb;

When a Verilog module is finished, it must be tested to ensure that it operates according to the machine specifications. The functionality of the module can be tested by applying stimulus to the inputs and checking the outputs. The test bench will display the inputs and outputs in a radix (binary, octal, hexadecimal, or decimal) as well as the waveforms.

1.1 Built-In Primitives

Logic primitives such as and, nand, or, nor, xor (exclusive-OR), and xnor (exclusive-NOR) functions are classified as multiple-input gates. The buf and not functions have one input, but can have one or more outputs. These are all built-in primitives that can be instantiated into a module. The inputs of built-in primitives are declared as type wire or as type reg depending on whether they were generated by a structural or behavioral module.

Type wire represents a physical connection between hardware elements. The output of a logic gate is declared as wire and represents a net with a single driver. The connection can be a wire or a group of wires, both of which are called a net. Nets are 1-bit scalar values unless declared otherwise.

Type reg data types are registers that hold a value. The register value is retained in memory until it is changed by a subsequent assignment. A variable of type reg closely resembles a hardware register that is synthesized with D flip-flops, JK flip-...

Table of contents

• Cover
• Half Title
• Title Page
• Copyright Page
• Dedication
• Table of Contents
• Preface
• Chapter 1 Introduction to Verilog HDL
• Chapter 2 Synthesis of Synchronous Sequential Machines 1 Using Verilog HDL
• Chapter 3 Synthesis of Synchronous Sequential Machines 2 Using Verilog HDL
• Chapter 4 Synthesis of Asynchronous Sequential Machines Using Verilog HDL
• Chapter 5 Synthesis of Pulse-Mode Asynchronous Sequential Machines Using Verilog HDL
• Appendix A Event Queue
• Appendix B Verilog Project Procedure
• Appendix C Answers to Select Problems
• Index