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ASAP7: A finFET-Based Framework for Academic VLSI Design at the 7 nm Node
Vinay Vashishtha and Lawrence T. Clark
CONTENTS
1.1 Introduction
1.1.1 Chapter Outline
1.2 ASAP7 Electrical Performance
1.3 Lithography Considerations
1.3.1 Lithography Metrics and Other Considerations for Design Rule Determination
1.3.1.1 Critical Dimension Uniformity (CDU)
1.3.1.2 Overlay
1.3.1.3 Mask Error Enhancement Factor (MEEF) and Edge Placement Error (EPE)
1.3.1.4 Time-Dependent Dielectric Breakdown (TDDB)
1.3.2 Single Exposure Optical Immersion Lithography
1.3.3 Multi-Patterning Approaches
1.3.3.1 Litho-Etchx (LEx)
1.3.3.2 Self-Aligned Multiple Patterning
1.3.3.3 Multiple Patterning Approach Comparison
1.3.4 Extreme Ultraviolet Lithography (EUVL)
1.3.4.1 EUVL Necessity
1.3.4.2 EUVL Description and Challenges
1.3.4.3 EUVL Advantages
1.3.5 Patterning Cliffs
1.3.6 DTCO
1.4 FEOL and MOL Layers
1.5 BEOL Layers
1.5.1 SAV and Barrier Layer
1.5.2 EUV Lithography Assumptions and Design Rules
1.5.3 MP Optical Lithography Assumptions and Design Rules
1.5.3.1 Patterning Choice
1.5.3.2 SADP Design Rules and Derivations
1.6 Cell Library Architecture
1.6.1 Gear Ratio and Cell Height
1.6.2 Fin Cut Implications
1.6.3 Standard Cell MOL Usage
1.6.4 Standard Cell Pin and Signal Routing
1.6.5 Library Collaterals
1.6.6 DTCO-Driven DR Changes Based on APR Results
1.7 Automated Place and Route with ASAP7
1.7.1 Power Routing and Self-Aligned Via (SAV)
1.7.2 Scaled LEF and QRC TechFile
1.7.3 Design Experiments and Results
1.8 SRAM Design
1.8.1 FinFET Implications and Fin Patterning
1.8.2 Statistical Analysis
1.8.3 SRAM Cell Design and DTCO Considerations
1.8.3.1 MOL Patterning
1.8.3.2 1-D Cell Metallization
1.8.3.3 Stability and Yield Analysis
1.8.4 Array Organization and Column Design
1.8.5 Write Assist
1.9 Chapter Summary
References
1.1 Introduction
Recent years have seen fin field-effect transistors (finFETs) dominate highly scaled, e.g., sub-20 nm, complementary metal-oxide-semiconductor (CMOS) processes (Wu et al., 2013; Lin et al., 2014) due to their ability to alleviate short channel effects, provide lower leakage, and enable some continued V DD scaling. However, the availability of a realistic finFET-based predictive process design kit (PDK) for academic use that supports investigation into both circuit as well as physical design, encompassing all aspects of digital design, has been lacking. While the finFET-based FreePDK15 was supplemented with a standard cell library, it lacked full physical verification, layout vs. schematic check (LVS) and parasitic extraction (Bhanushali et al., 2015; Martins et al., 2015). Consequently, the only available sub-45 nm educational PDKs are the planar CMOS-based Synopsys 32/28 nm and FreePDK45 (45 nm PDK) (Goldman et al., 2013; Stine et al., 2007). The cell libraries available for those processes are not very realistic since they use very large cell heights, in contrast to recent industry trends. Additionally, the static random access memory (SRAM) rules and cells provided by these PDKs are not realistic. Because finFETs have a three-dimensional (3-D) structure and there have been significant density impacts in their adoption, using planar libraries scaled to sub-22 nm dimensions for research is likely to give poor accuracy.
Commercial libraries and PDKs, especially for advanced nodes, are often difficult to obtain for academic use, and access to the actual physical layouts is even more restricted. Furthermore, the necessary non-disclosure agreements (NDAs) are unmanageable for large university classes and the plethora of design rules (DRs) can distract from the key points. NDAs also make it difficult for the publication of physical design as these may disclose proprietary DRs and structures.
This chapter focuses on the development of a realistic PDK for academic use that overcomes these limitations. The PDK, developed for the N7 node before 7 nm processes were available even in industry, is thus predictive. The predictions have been based on publications of the continually improving lithography, as well as our estimates of what would be available at N7. The original assumptions are described in Clark et al. (2016). For the most part, these assumptions have been accurate, except for the expectation that extreme ultraviolet lithography (EUVL) would be widely available, which has turned out to be optimistic. The background and impact on design technology co-optimization (DTCO) for standard cells and SRAM comprise this chapter. The treatment here includes learning from using the cells originally derived in Clark et al. (2016) in realistic designs of SRAM arrays and large digital designs using automated place and route tools.
1.1.1 Chapter Outline
The chapter first outlines the important lithography considerations in Section 1.3. Metrics for overlay, mask errors and other effects that limit are described first. Then, modern liquid immersion optical lithography and its use in multiple patterning (MP) techniques that extend it beyond the standard 80 nm feature limit are discussed. This sets the stage for a discussion of EUV lithography, which can expose features down to about 16 nm in a single exposure (SE), but at a high capital and throughput cost. This section ends with a brief overview of DTCO. DTCO has been required on recent processes to ensure that the very limited possible structures that can be practically fabricated are usable to build real designs. Thus, a key part of a process development is not just to determine transistor and interconnect structures that are lithographically possible, but also to ensure that successful designs can be built with those structures. This discussion is carried out by separating the front end of line (FEOL), middle of line (MOL), and back end of line (BEOL) portions of the process, which fabricate the transistors, contacts and local interconnect, and global interconnect metallization, respectively. The cell library architecture and automated placement and routing (APR) aspects comprise the next section, which with the SRAM results comprise most of the discussion. The penultimate section describes the SRAM DTCO and array development and performance in the ASAP7 predictive PDK. The final section summarizes.
1.2 ASAP7 Electrical Performance
The PDK uses BSIM-CMG SPICE models and the values used are derived from publicly available sources with appropriate assumptions (Paydavosi et al., 2013). A drive current increase from 14 to 7 nm node is assumed to be 15%, which corresponds to the diminished I dsat improvement over time. In accordance with modern devices, the saturation current is assumed to be 4.5× larger than that in the linear region (Clark et al., 2016). A relaxed 54 nm contacted poly pitch (CPP) allows a longer channel length and helps with the assumption of a near ideal subthreshold slope (SS) of 60 mV/decade at room temperature, along with a drain-induced barrier lowering (DIBL) of approximately 30 mV/V. P-type metal-oxide semiconductor (PMOS) strain seems to be easier to obtain according to the 16 and 14 nm foundry data and larger I dsat values for PMOS than those for a n-type metal-oxide semiconductor (NMOS) have been reported (Wu et al., 2013; Lin et al., 2014). Following this trend, we assume a PMOS-to-NMOS drive ratio of 0.9:1. This value provides good slew rates at a fan-out of six (FO6), instead of the traditional four.
Despite the same drawn gate length, the PDK and library timing abstract views support four threshold voltage flavors, viz. super low voltage threshold (SLVT), low voltage threshold (LVT), regular threshold voltage (RVT), and SRAM, to allow investigation into both high-performance and low-power designs. The threshold voltage is assumed to be changed through work function engineering. For SRAM devices, the very low leakage uses both a work function change and lightly doped drain (LDD) implant removal. The latter results in an effective channel length (Leff) increase, gate-induced drain leakage (GIDL) reduction, and an overlap capacitance reduction. The drive strength reduces from SLVT to SRAM. The SRAM V th transistors are a convenient option for use in retention latches and designs that prioritize low-standby power. In addition to typical-typical (TT) models, fast-fast (FF) and slow-slow (SS) models are also provided for multi-corner APR optimization. Tables 1.1 and 1.2 show the electrical parameters for single fin NMOS and PMOS, r...
