Advanced VLSI Design and Testability Issues

Suman Lata Tripathi, Sobhit Saxena, Sushanta Kumar Mohapatra, Suman Lata Tripathi, Sobhit Saxena, Sushanta Kumar Mohapatra

• Publisher: CRC Press
• Year: 2020
• Print ISBN: 9780367538361
• eBook ISBN: 9781000168174
• Topic: Technology & Engineering
• Subtopic: Electrical Engineering & Telecommunications
• Index: Technology & Engineering

This book facilitates the VLSI-interested individuals with not only in-depth knowledge, but also the broad aspects of it by explaining its applications in different fields, including image processing and biomedical. The deep understanding of basic concepts gives you the power to develop a new application aspect, which is very well taken care of in this book by using simple language in explaining the concepts. In the VLSI world, the importance of hardware description languages cannot be ignored, as the designing of such dense and complex circuits is not possible without them. Both Verilog and VHDL languages are used here for designing. The current needs of high-performance integrated circuits (ICs) including low power devices and new emerging materials, which can play a very important role in achieving new functionalities, are the most interesting part of the book. The testing of VLSI circuits becomes more crucial than the designing of the circuits in this nanometer technology era. The role of fault simulation algorithms is very well explained, and its implementation using Verilog is the key aspect of this book.

This book is well organized into 20 chapters. Chapter 1 emphasizes on uses of FPGA on various image processing and biomedical applications. Then, the descriptions enlighten the basic understanding of digital design from the perspective of HDL in Chapters 2–5. The performance enhancement with alternate material or geometry for silicon-based FET designs is focused in Chapters 6 and 7. Chapters 8 and 9 describe the study of bimolecular interactions with biosensing FETs. Chapters 10–13 deal with advanced FET structures available in various shapes, materials such as nanowire, HFET, and their comparison in terms of device performance metrics calculation. Chapters 14–18 describe different application-specific VLSI design techniques and challenges for analog and digital circuit designs. Chapter 19 explains the VLSI testability issues with the description of simulation and its categorization into logic and fault simulation for test pattern generation using Verilog HDL. Chapter 20 deals with a secured VLSI design with hardware obfuscation by hiding the IC's structure and function, which makes it much more difficult to reverse engineer.

Table of contents

• Cover
• Half Title
• Title Page
• Copyright Page
• Table of Contents
• Preface to the First Edition
• Editors
• Contributors
• Chapter 1 Digital Design with Programmable Logic Devices
• Chapter 2 Review of Digital Electronics Design
• Chapter 3 Verilog HDL for Digital and Analog Design
• Chapter 4 Introduction to Hardware Description Languages
• Chapter 5 Introduction to Hardware Description Languages (HDLs)
• Chapter 6 Emerging Trends in Nanoscale Semiconductor Devices
• Chapter 7 Design Challenges and Solutions in CMOS-Based FET
• Chapter 8 Analytical Design of FET-Based Biosensors
• Chapter 9 Low-Power FET-Based Biosensors
• Chapter 10 Nanowire Array–Based Gate-All-Around MOSFET for Next-Generation Memory Devices
• Chapter 11 Design of 7T SRAM Cell Using FinFET Technology
• Chapter 12 Performance Analysis of AlGaN/GaN Heterostructure Field-Effect Transistor (HFET)
• Chapter 13 Synthesis of Polymer-Based Composites for Application in Field-Effect Transistors
• Chapter 14 Power Efficiency Analysis of Low-Power Circuit Design Techniques in 90-nm CMOS Technology
• Chapter 15 Macromodeling and Synthesis of Analog Circuits
• Chapter 16 Performance-Linked Phase-Locked Loop Architectures: Recent Developments
• Chapter 17 Review of Analog-to-Digital and Digital-to-Analog Converters for A Smart Antenna Application
• Chapter 18 Active Inductor–Based VCO for Wireless Communication
• Chapter 19 Fault Simulation Algorithms: Verilog Implementation
• Chapter 20 Hardware Protection through Logic Obfuscation
• Index