VHDL 101

Everything you Need to Know to Get Started

William Kafig

• Publisher: Newnes
• Year: 2011
• Print ISBN: 9781856177047
• eBook ISBN: 9780080959399
• Topic: Ciencia de la computación
• Subtopic: Lenguajes de programación

VHDL 101 is written for Electrical Engineers and others wishing to break into FPGA design and assumes a basic knowledge of digital design and some experience with engineering 'process'.Bill Kafig, industry expert, swiftly brings the reader up to speed on techniques and functions commonly used in VHDL (VHSIC Hardware Description Language) as well as commands and data types. Extensive simple, complete designs accompany the content for maximum comprehension. The book concludes with a section on design re-use, which is of utmost importance to today's engineer who needs to meet a deadline and lower costs per unit.*Gets you up to speed with VHDL fast, reducing time to market and driving down costs*Covers the basics including language concepts and includes complete design examples for ease of learning* Covers widely accepted industry nomenclature* Learn from "best design practices"- Gets you up to speed with VHDL fast, reducing time to market and driving down costs- Covers the basics including language concepts and includes complete design examples for ease of learning- Covers widely accepted industry nomenclature- Learn from "best design practices"

Chapter 1. Introduction and Background

1.1. VHDL

VHDL. Four little letters. So much to understand.

There are many approaches to learning the Very-High-Speed Integrated Circuit Hardware Description Language (VHDL). These range from the academic – where each piece is looked at, turned upside down and inside out, and fully understood at an atomic level, yet only a few understand how to actually USE the language to implement a design; to OJT¹ where an engineer may be handed either poorly written code (or in rare cases a well written piece of code), or nothing at all and told that they are now responsible for the Field Programmable Gate Array (FPGA) in the system.

¹On-The-Job-Training, most often this is a “sink-or-swim” scenario. Without a framework, engineers who learn in this style often code inefficiently.

Somewhere in between lays a happy medium – a way to learn VHDL and be productive as quickly as possible.

I have a strong background in the Japanese Martial Art of Aikido. Like so many Martial Arts there are “beginning techniques”, “intermediate techniques”, and “advanced techniques”, yet all of them are built on certain fundamental ideas of movement. It would be a disservice to a student to spend hundreds of hours on wrist techniques alone without covering falling techniques (one way to avoid harm), or posture, or any number of other important aspects of the Art.

We start out simply, get a rough idea of what we're in for – sort of a sampling of the various aspects, but none in any great detail.

Now that the student has an idea of what he's in for, he² has a better idea of what lies ahead so that the next iteration of falling, arm techniques, wrist techniques, knee work, etc., there is a context in which to place the learning. In this fashion, an upward spiral of success is achieved.

²I use “he” instead of the awkward “he/she” or the more encompassing “he/she/he–she/she–he/it”. This is not out of sexism, but out of long tradition, in virtually every language, of using the third person masculine for when the gender of the reader is unknown (as opposed to indeterminate).

I'd like to take you on this same path in VHDL. We'll start out by traversing the general process of developing an FPGA. ³ During this process you will encounter “forward references”, that is, references to aspects of VHDL that we haven't covered yet. Currently, there is no known way to avoid this problem except through a highly academic, “atomic” view of the language, with no references or context relative to other aspects or commands of the language. This is exactly what we are attempting to AVOID. When you see a new construct, there will be a brief conceptual description of what it does and the details will be provided later.

³Although the focus of this book is VHDL, I believe that a brief overview of the entire flow helps create a context in which to place this learning.

Once we've made our first “loop” through the material, we'll revisit the initial concepts and statement and begin adding to it and exploring the capabilities of the language. We'll also begin looking at some of the synthesis tool's capabilities and how to verify that the code is behaving properly prior to testing it in silicon (i.e. simulation).

The focus of this book is on VHDL which is one of the primary FPGA languages, but who wants to work in a vacuum? References to various tools and other languages are made to help the reader better understand the landscape into which he is entering. The Xilinx tools will only be covered to the extent that they are required to produce a viable netlist and for simulation. Other books, websites and classes from the FPGA vendors delve into great detail as to how the various tools can be effectively applied.

This book is, by no means, the end-all, be-all reference for VHDL. The intention is to convey the basic principles of VHDL with a smattering of FPGA techniques so that the VHDL has relevance and so that you can get started coding quickly. In that vein neither every aspect of VHDL is covered, nor are the covered aspects detailed to the nth degree – but they are covered enough to get you coding for FPGAs very quickly.

There are a number of very good, extremely detailed books out there – look for anything written by Peter Ashenden.

1.2. Brief History of VHDL

Way back, in the BEFORE TIME, say around 1981, the US Department of Defense began writing the specifications for the Very-High-Speed Integrated Circuit (VHSIC) program. The intent was to be able to accurately and thoroughly describe the behavior of circuits for documentation, simulation, and (later) synthesis purposes. This initiative was known as VHDL. July of 1983 saw Intermetics, IBM, and Texas Instruments begin developing the first version of VHDL, which was finally released in August of 1985.

Just to flesh out the timeline, Xilinx invented the first FPGA in 1984, began shipping parts in 1985, and was supporting VHDL shortly thereafter using a third-party synthesis tool.

Due to the popularity of the language, the Institute of Electrical and Electronics Engineers (IEEE) convened a committee to formalize the language. This task was completed in 1987 and the standard became known as IEEE 1076-1987. This standard has been revisited a number of times (1993 and 2000) since then, and the current standard IEEE 1076-2008 is known informally as VHDL-2008. As this latest standard has not yet been ratified (at the time of writing), we will use the IEEE 1076-2000 standard which tends to be a superset of previous versions.

VHDL is a large, complex, and powerful language. Although the language is feature-rich, many designs only require a small subset of the total capabilities.

As a Department of Defense (DoD) project where, quite literally, lives were at stake, no aspect of VHDL would be assumed and it was deigned to be a “strongly typed” language, sharing many concepts and features with the programming language Ada.

VHDL gained very rapid acceptance (as it was mandated by DoD of their agencies and contractors), initially on the East Coast. This is in contrast to Verilog, another FPGA “programming” language, which began its life as a programming language for Application Specific Integrated Circuits (ASICs) and is particularly strong on the West Coast.

VHDL's history still weighs on the current implementation, most notably in the “process sensitivity list” used for simulation. At the time that VHDL was developed, the then “brand new” PC class machines were running at 5 MHz and 640 KB of memory. Processor cycles were very expensive! So, in order not to waste processor time, the process sensitivity list was examined to see if key signals had changed since the last iteration. If so, the block of code was executed, otherwise it was skipped. This is one of the places where some problems of today can occur as the synthesis tools ignore the process sensitivity list and we encounter an error known as “simulation mismatch”.

1.2.1. Coding Styles: Structural vs. Behavioral vs. RTL

You may hear several adjectives used with VHDL – Structural VHDL, Behavioral VHDL, RTL coding, etc. These are not separate languages, but rather different approaches to coding. These method...

Table of contents

• Cover Image
• Table of Contents
• Front Matter
• Copyright
• Preface
• About the Author
• Acknowledgments
• Chapter 1. Introduction and Background
• Chapter 2. Overview of the Process of Implementing an FPGA Design
• Chapter 3. Loop 1 – Going with the Flow
• Chapter 4. Loop 2 – Going Deeper
• Chapter 5. Loop 3
• Appendix. A Quick Reference
• Index