The Definitive Guide to ARM® Cortex®-M3 and Cortex®-M4 Processors

Joseph Yiu

• Publisher: Newnes
• Year: 2013
• eBook ISBN: 9780124079182
• Edition: 3
• Topic: Computer Science
• Subtopic: Hardware
• Index: Computer Science

This new edition has been fully revised and updated to include extensive information on the ARM Cortex-M4 processor, providing a complete up-to-date guide to both Cortex-M3 and Cortex-M4 processors, and which enables migration from various processor architectures to the exciting world of the Cortex-M3 and M4. This book presents the background of the ARM architecture and outlines the features of the processors such as the instruction set, interrupt-handling and also demonstrates how to program and utilize the advanced features available such as the Memory Protection Unit (MPU). Chapters on getting started with IAR, Keil, gcc and CooCox CoIDE tools help beginners develop program codes. Coverage also includes the important areas of software development such as using the low power features, handling information input/output, mixed language projects with assembly and C, and other advanced topics. - Two new chapters on DSP features and CMSIS-DSP software libraries, covering DSP fundamentals and how to write DSP software for the Cortex-M4 processor, including examples of using the CMSIS-DSP library, as well as useful information about the DSP capability of the Cortex-M4 processor - A new chapter on the Cortex-M4 floating point unit and how to use it - A new chapter on using embedded OS (based on CMSIS-RTOS), as well as details of processor features to support OS operations - Various debugging techniques as well as a troubleshooting guide in the appendix - Topics on software porting from other architectures - A full range of easy-to-understand examples, diagrams and quick reference appendices

Chapter 1

Introduction to ARM^® Cortex^®-M Processors

Abstract

Overview of the ARM^® Cortex^®-M3 and Cortex-M4 processors, and the whole Cortex-M processor family. Differences between processors and microcontrollers. Resources which are useful, and background about ARM and ARM processor products.

Keywords

ARM; Cortex-M; microcontroller; background; resources; technical advantages

Chapter Outline

1.1 What are the ARM^® Cortex^®-M processors?

1.1.1 The Cortex^®-M3 and Cortex-M4 processors

1.1.2 The Cortex^®-M processor family

1.1.3 Differences between a processor and a microcontroller

1.1.4 ARM^® and the microcontroller vendors

1.1.5 Selecting Cortex^®-M3 and Cortex-M4 microcontrollers

1.2 Advantages of the Cortex^®-M processors

1.2.1 Low power

1.2.2 Performance

1.2.3 Energy efficiency

1.2.4 Code density

1.2.5 Interrupts

1.2.6 Ease of use, C friendly

1.2.7 Scalability

1.2.8 Debug features

1.2.9 OS support

1.2.10 Versatile system features

1.2.11 Software portability and reusability

1.2.12 Choices (devices, tools, OS, etc.)

1.3 Applications of the ARM^® Cortex^®-M processors

1.4 Resources for using ARM^® processors and ARM microcontrollers

1.4.1 What can you find on the ARM^® website

1.4.2 Documentation from the microcontroller vendors

1.4.3 Documentation from tool vendors

1.4.4 Other resources

1.5 Background and history

1.5.1 A brief history of ARM^®

1.5.2 ARM^® processor evolution

1.5.3 Architecture versions and Thumb^® ISA

1.5.4 Processor naming

1.5.5 About the ARM^® ecosystem

1.1 What are the ARM^® Cortex^®-M processors?

1.1.1 The Cortex^®-M3 and Cortex-M4 processors

The Cortex^®-M3 and Cortex-M4 are processors designed by ARM^®. The Cortex-M3 processor was the first of the Cortex generation of processors, released by ARM in 2005 (silicon products released in 2006). The Cortex-M4 processor was released in 2010 (released products also in 2010).

The Cortex-M3 and Cortex-M4 processors use a 32-bit architecture. Internal registers in the register bank, the data path, and the bus interfaces are all 32 bits wide. The Instruction Set Architecture (ISA) in the Cortex-M processors is called the Thumb^® ISA and is based on Thumb-2 Technology which supports a mixture of 16-bit and 32-bit instructions.

The Cortex-M3 and Cortex-M4 processors have:

• Three-stage pipeline design

• Harvard bus architecture with unified memory space: instructions and data use the same address space

• 32-bit addressing, supporting 4GB of memory space

• On-chip bus interfaces based on ARM AMBA^® (Advanced Microcontroller Bus Architecture) Technology, which allow pipelined bus operations for higher throughput

• An interrupt controller called NVIC (Nested Vectored Interrupt Controller) supporting up to 240 interrupt requests and from 8 to 256 interrupt priority levels (dependent on the actual device implementation)

• Support for various features for OS (Operating System) implementation such as a system tick timer, shadowed stack pointer

• Sleep mode support and various low power features

• Support for an optional MPU (Memory Protection Unit) to provide memory protection features like programmable memory, or access permission control

• Support for bit-data accesses in two specific memory regions using a feature called Bit Band

• The option of being used in single processor or multi-processor designs

The ISA used in Cortex-M3 and Cortex-M4 processors provides a wide range of instructions:

• General data processing, including hardware divide instructions

• Memory access instructions supporting 8-bit, 16-bit, 32-bit, and 64-bit data, as well as instructions for transferring multiple 32-bit data

• Instructions for bit field processing

• Multiply Accumulate (MAC) and saturate instructions

• Instructions for branches, conditional branches and function calls

• Instructions for system control, OS support, etc.

In addition, the Cortex-M4 processor also supports:

• Single Instruction Multiple Data (SIMD) operations

• Additional fast MAC and multiply instructions

• Saturating arithmetic instructions

• Optional floating point instructions (single precision)¹

Both the Cortex-M3 and Cortex-M4 processors are widely used in modern microcontroller products, as well as other specialized silicon designs such as System on Chips (SoC) and Application Specific Standard Products (ASSP).

In general, the ARM Cortex-M processors are regarded as RISC (Reduced Instruction Set Computing) processors. Some might argue that certain characteristics of the Cortex-M3 and Cortex-M4 processors, such as the rich instruction set and mixed instruction sizes, are closer to CISC (Complex Instruction Set Computing) processors. But as processor technologies advance, the instruction sets of most RISC processors are also getting more complex, so much so that this traditional boundary between RISC and CISC processor definition can no longer be applied.

There are a lot of similarities between the Cortex-M3 and Cortex-M4 processors. Most of the instructions are available on both processors, and the processors have the same programmer’s model for NVIC, MPU, etc. However, there are some differences in their internal designs, which allow the Cortex-M4 processor to deliver higher performance in DSP applications, and to support floating point operations. As a result, some of the instructions available on both processors can be executed in fewer clock cycles on the Cortex-M4.

1.1.2 The Cortex^®-M processor family

The Cortex^®-M3 and Cortex-M4 processors are two of the products in the ARM^® Cortex-M processor family. The whole Cortex-M processor family is shown in Figure 1.1.

FIGURE 1.1 The Cortex-M processor family

The Cortex-M3 and Cortex-M4 processors are based on ARMv7-M architecture. Both are high-performance processors that are designed for microcontrollers. Because the Cortex-M4 processor has SIMD, fast MAC, and saturate arithmetic instructions, it can also carry out some of the digital signal processing applications that traditionally have been carried out by a separate Digital Signal Processor (DSP).

The Cortex-M0, Cortex-M0+, and the Cortex-M1 processors are based on ARMv6-M, which has a smaller instruction set. Both Cortex-M0 and Cortex-M0+ are very small size in terms of gate count, with just about 12K gates² in minimum configuration, and are ideal for low-cost microcontroller products. The Cortex-M0+ processor has the most state-of-the-art low power optimizations, and has more available optional features.

The Cortex-M1 processor is designed specifically for FPGA applications. It has Tightly Coupled Memory (TCM) features that can be implemented using memories inside the FPGA, and the design allows high clock frequency operations in advanced FPGA. For example, it can run at over 200 MHz in Altera Stratix III FPGA.

For general data processing and I/O control tasks, the Cortex-M0 and Cortex-M0+ processors have excellent energy efficiency due to the low gate count design. But for applications with complex data processi...

Table of contents

• Cover image
• Title page
• Table of Contents
• Copyright
• Foreword
• Preface
• Synopsis
• About this Book
• Contributor Bio-Paul Beckmann
• Acknowledgments
• Terms and Abbreviations
• Conventions
• Chapter 1. Introduction to ARM® Cortex®-M Processors
• Chapter 2. Introduction to Embedded Software Development
• Chapter 3. Technical Overview
• Chapter 4. Architecture
• Chapter 5. Instruction Set
• Chapter 6. Memory System
• Chapter 7. Exceptions and Interrupts
• Chapter 8. Exception Handling in Detail
• Chapter 9. Low Power and System Control Features
• Chapter 10. OS Support Features
• Chapter 11. Memory Protection Unit (MPU)
• Chapter 12. Fault Exceptions and Fault Handling
• Chapter 13. Floating Point Operations
• Chapter 14. Introduction to the Debug and Trace Features
• Chapter 15. Getting Started with Keil Microcontroller Development Kit for ARM®
• Chapter 16. Getting Started with the IAR Embedded Workbench for ARM®
• Chapter 17. Getting Started with the GNU Compiler Collection (gcc)
• Chapter 18. Input and Output Software Examples
• Chapter 19. Using Embedded Operating Systems
• Chapter 20. Assembly and Mixed Language Projects
• Chapter 21. ARM® Cortex®-M4 and DSP Applications
• Chapter 22. Using the ARM® CMSIS-DSP Library
• Chapter 23. Advanced Topics
• Chapter 24. Software Porting
• References
• Index
• Appendix A. Instruction Set Summary
• Appendix B. Graphical Representations of DSP Instructions
• Appendix C. Addition of 16-bit Thumb® Instructions in Recent Architecture Versions
• Appendix D. Cortex®-M3/M4 Exceptions Quick Reference
• Appendix E. CMSIS-Core Functions Quick Reference
• Appendix F. NVIC and SCB Registers Quick Reference
• Appendix G. Cortex®-M3/M4 Debug Components Programmer’s Model
• Appendix H. Connectors for Debug and Trace
• Appendix I. Troubleshooting Guide