Advances in Chemical Mechanical Planarization (CMP)

Babu Suryadevara

• Publisher: Woodhead Publishing
• Year: 2016
• eBook ISBN: 9780081002186
• Topic: Technology & Engineering
• Subtopic: Electrical Engineering & Telecommunications
• Index: Technology & Engineering

Advances in Chemical Mechanical Planarization (CMP) provides the latest information on a mainstream process that is critical for high-volume, high-yield semiconductor manufacturing, and even more so as device dimensions continue to shrink. The technology has grown to encompass the removal and planarization of multiple metal and dielectric materials and layers both at the device and the metallization levels, using different tools and parameters, requiring improvements in the control of topography and defects. This important book offers a systematic review of fundamentals and advances in the area. Part One covers CMP of dielectric and metal films, with chapters focusing on the use of particular techniques and processes, and on CMP of particular various materials, including ultra low-k materials and high-mobility channel materials, and ending with a chapter reviewing the environmental impacts of CMP processes. Part Two addresses consumables and process control for improved CMP, and includes chapters on the preparation and characterization of slurry, diamond disc pad conditioning, the use of FTIR spectroscopy for characterization of surface processes, and approaches for defection characterization, mitigation, and reduction. - Considers techniques and processes for CMP of dielectric and metal films - Includes chapters devoted to CMP for particular materials - Addresses consumables and process control for improved CMP

Part One

CMP of dielectric and metal films

Outline

1. Chemical and physical mechanisms of dielectric chemical mechanical polishing (CMP)

2. Copper chemical mechanical planarization (Cu CMP) challenges in 22 nm back-end-of-line (BEOL) and beyond

3. Electrochemical techniques and their applications for chemical mechanical planarization (CMP) of metal films

4. Ultra low-k materials and chemical mechanical planarization (CMP)

5. CMP processing of high mobility channel materials: alternatives to Si

6. Multiscale modeling of chemical mechanical planarization (CMP)

7. Polishing of SiC films

8. Chemical and physical mechanisms of CMP of gallium nitride

9. Abrasive-free and ultra-low abrasive chemical mechanical polishing (CMP) processes

10. Environmental aspects of planarization processes

1

Chemical and physical mechanisms of dielectric chemical mechanical polishing (CMP)

Y. Moon Advanced Technology Development (ATD), GLOBALFOUNDRIES, Malta, NY, USA

Abstract

Dielectric chemical mechanical polishing (CMP) was implemented in semiconductor fabrication as a simple alternative planarization process for the interlevel dielectrics surface instead of the reactive ion etching process of the 1980s. Since then, there have been a growing number of applications of the dielectric CMP process in advanced semiconductor fabrication because of multiple “new” integration schemes (such as replacement metal gate (RMG), or self-aligned contact), which require advanced planarization technology. It is important to understand its history, material removal mechanism, defect formation, and present and future applications to comprehend why dielectric CMP has to be used, how the material is removed, and how the defect is created. By understanding what has been studied on the current dielectric CMP process, future applications of dielectric CMP can be further improved for better process performance and, therefore, for better device performance and yield.

Keywords

Chemical mechanical planarization; Chemical mechanical polishing (CMP); Interlevel dielectrics (ILD); Oxide CMP; Semiconductor fabrication

1.1. Introduction

A dielectric material is an electrical insulator (such as silicon dioxide), which is widely used in semiconductor fabrication. In shallow trench isolation (STI), dielectric material separates the two transistors by being located between two devices. In the interlevel dielectric (ILD) layer, a dielectric separates the whole device region from the metallization layer as an independent layer located between the front-end-of-line (FEOL) and back-end-of-line (BEOL). Dielectric chemical mechanical polishing (CMP) is the CMP process that will polish and planarize dielectrics. Dielectric CMP is the first CMP process used in modern microdevice fabrication and the most widely used among all the CMP processes in memory devices as well as in logic devices in semiconductor manufacturing. In this chapter, the dielectric CMP is reviewed from its material removal mechanisms to its applications in semiconductor fabrication. It is important to understand its history, its motivation to use, and its future application in advanced semiconductor technology.

1.2. History of dielectric CMP

CMP or planarization is a relatively new fabrication technology in semiconductor manufacturing, compared to lithography, etching, or thin film deposition technology. The concept of polishing has been used for centuries for optics fabrication. In the early 1950s, polishing was implemented in preparing silicon wafer substrate to minimize any surface damage [1,2]. In the 1980s, polishing was used as part of the integrated circuit fabrication process to planarize the ILD surface instead of reactive ion etching (RIE) technology [3], and the first technical paper on CMP was published in the late 1980s [4]. Since then, ILD CMP has become the process of choice for ILD planarization and the role of the CMP process has expanded to other applications such as STI, tungsten contact formation, or copper metallization by damascene technology.

In the advanced semiconductor technology node, dielectric CMP is no longer a simple dielectric planarization process. The applications of dielectric CMP technology further extended to multiple modules to enable critical integration schemes such as replacement metal gate (RMG), multigate transistor, or self-aligned contact (SAC) modules. In particular, since CMP's use in gate formation, the technological requirement from the dielectric CMP process went beyond what the conventional dielectric CMP process was able to deliver. The number of CMP processes in advanced semiconductor manufacturing has also expanded up to 20–30 steps because of RMG and fin formation (Figure 1.1).

Figure 1.1 CMP applications in advanced logic technology [5,13].

In order to meet this stringe...

Table of contents

• Cover image
• Title page
• Table of Contents
• Related titles
• Copyright
• List of contributors
• Woodhead Publishing Series in Electronic and Optical Materials
• Introduction
• Part One. CMP of dielectric and metal films
• Part Two. Consumables and process control for improved CMP
• Index