System-on-Chip Test Architectures

Nanometer Design for Testability

Laung-Terng Wang, Charles E. Stroud, Nur A. Touba

• Publisher: Morgan Kaufmann
• Year: 2010
• Print ISBN: 9780123739735
• eBook ISBN: 9780080556802
• Topic: Design
• Subtopic: Industrial Design

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.- Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.- Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.- Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.- Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.- Practical problems at the end of each chapter for students.

Table of contents

• Front Cover
• System-on-Chip Test Architectures
• Copyright Page
• Table of Contents
• Preface
• In the Classroom
• Acknowledgments
• Contributors
• About the Editors
• Chapter 1 Introduction
• Chapter 2 Digital Test Architectures
• Chapter 3 Fault-Tolerant Design
• Chapter 4 System/Network-on-Chip Test Architectures
• Chapter 5 SIP Test Architectures
• Chapter 6 Delay Testing
• Chapter 7 Low-Power Testing
• Chapter 8 Coping with Physical Failures, Soft Errors, and Reliability Issues
• Chapter 9 Design for Manufacturability and Yield
• Chapter 10 Design for Debug and Diagnosis
• Chapter 11 Software-Based Self-Testing
• Chapter 12 Field Programmable Gate Array Testing
• Chapter 13 MEMS Testing
• Chapter 14 High-Speed I/O Interfaces
• Chapter 15 Analog and Mixed-Signal Test Architectures
• Chapter 16 RF Testing
• Chapter 17 Testing Aspects of Nanotechnology Trends
• Index