ASIC and FPGA Verification

A Guide to Component Modeling

Richard Munden

• Publisher: Morgan Kaufmann
• Year: 2004
• Print ISBN: 9780125105811
• eBook ISBN: 9780080475929
• Topic: Computer Science
• Subtopic: Data Modelling & Design
• Index: Computer Science

Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today's digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. - Provides numerous models and a clearly defined methodology for performing board-level simulation - Covers the details of modeling for verification of both logic and timing - First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification

Table of contents

• Front cover
• ABOUT THE AUTHOR
• Title page
• Copyright Page
• Table of Contents
• PREFACE
• PART I INTRODUCTION
• PART II RESOURCES AND STANDARDS
• PART III MODELING BASICS
• PART IV ADVANCED MODELING
• Index