
- 286 pages
- English
- PDF
- Available on iOS & Android
High-Level Language Computer Architecture
About this book
High-Level Language Computer Architecture offers a tutorial on high-level language computer architecture, including von Neumann architecture and syntax-oriented architecture as well as direct and indirect execution architecture. Design concepts of Japanese-language data processing systems are discussed, along with the architecture of stack machines and the SYMBOL computer system. The conceptual design of a direct high-level language processor is also described. Comprised of seven chapters, this book first presents a classification of high-level language computer architecture according to the proximity of the machine language and the programming language. This classification gives four types: von Neumann architecture, syntax-oriented architecture, indirect execution architecture, and direct execution architecture. In order to illustrate the possible evolution of computer architecture, design concepts of Japanese-language data processing systems are chosen as an example. Subsequent chapters focus on the syntax-oriented architecture; the historical SYMBOL computer system which makes use of an indirect execution architecture; and design concepts of direct-execution architecture for the ALGOL 60 language. The final chapter describes the architecture for the processor for an APL subset. This monograph will be of interest to specialists in electronics and computer science.
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Information
Table of contents
- Front Cover
- High-Level Language Computer Architecture
- Copyright Page
- Table of Contents
- List of Contributors
- Preface
- Chapter 1. Concepts of High-Level Language Computer Architecture
- Chapter 2. Design Concepts of Japanese-Language Data Processing Systems
- Chapter 3. A Survey of High-Level Language Computer Architecture
- Chapter 4. Architecture of Stack Machines
- Chapter 5. Architecture of the SYMBOL Computer System
- Chapter 6. Conceptual Design of a Direct High-Level Language Processor
- Chapter 7. Architectural Design of an APL Processor
- Index