Electrical and Electronic Devices, Circuits and Materials

Design and Applications

Suman Lata Tripathi, Parvej Ahmad Alvi, Umashankar Subramaniam

• Publisher: CRC Press
• Year: 2021
• Print ISBN:
  9780367564261
• eBook ISBN:
  9781000330090
• Topic: Technology & Engineering
• Subtopic: Electrical Engineering & Telecommunications
• Index: Technology & Engineering

The increasing demand in home and industry for electronic devices has encouraged designers and researchers to investigate new devices and circuits using new materials that can perform several tasks efficiently with low IC (integrated circuit) area and low power consumption. Furthermore, the increasing demand for portable devices intensifies the search to design sensor elements, an efficient storage cell, and large-capacity memory elements. Electrical and Electronic Devices, Circuits and Materials: Design and Applications will assist the development of basic concepts and fundamentals behind devices, circuits, materials, and systems. This book will allow its readers to develop their understanding of new materials to improve device performance with even smaller dimensions and lower costs. Additionally, this book covers major challenges in MEMS (micro-electromechanical system)-based device and thin-film fabrication and characterization, including their applications in different fields such as sensors, actuators, and biomedical engineering.

Key Features:

• Assists researchers working on devices and circuits to correlate their work with other requirements of advanced electronic systems.
• Offers guidance for application-oriented electrical and electronic device and circuit design for future energy-efficient systems.
• Encourages awareness of the international standards for electrical and electronic device and circuit design.

Organized into 23 chapters, Electrical and Electronic Devices, Circuits and Materials: Design and Applications will create a foundation to generate new electrical and electronic devices and their applications. It will be of vital significance for students and researchers seeking to establish the key parameters for future work.

1 MOSFET Design and Its Optimization for Low-Power Applications

P. Vimala

Dayananda Sagar College of Engineering

M. Karthigai Pandian

Sri Krishna College of Technology

T. S. Arun Samuel

National Engineering College

Contents

1.1 Introduction

1.2 VLSI Design Hierarchy

1.3 MOSFET Basics

1.3.1 NMOS Enhancement Mode MOSFET Operation

1.4 Compact Models for MOSFET

1.5 CMOS Technology and Scaling

1.6 Short Channel Effects

1.7 Silicon-on-Insulator (SOI) MOSFET

1.8 Multi-Gate MOSFETs

1.9 Silicon Nanowire Transistors

1.9.1 Rectangular Surrounding Gate Silicon Nanowire Transistors

1.9.2 Junctionless Cylindrical Surrounding Gate Nanowire Transistors

1.10 Tunnel Field Effect Transistors

1.10.1 Multi-Gate Tunnel FETs

1.10.1.1 Double Gate TFETs

1.10.1.2 Dual Material Double Gate TFETs

1.10.1.3 DG and DMDG TFETs with SiO₂/High-k Stacked Gate-Oxide Structure

1.10.1.4 Tri-Gate SOI TFETs

1.10.1.5 Heterojunction Triple Material DG TFETs

1.11 Summary

References

1.1 Introduction

Metal-Oxide Semiconductor Field Effect Transistors (MOSFETs) find a major role in digital circuits because of their better efficiency in terms of power consumption and reduced silicon-area usage compared to bipolar digital technologies. In the current scenario, they are the basic building blocks of integrated circuits (ICs) and microprocessors. Continuous development of CMOS technology is guided and improved by CMOS scaling. As the size of the devices is reduced to greater proportions, their switching capabilities tend to get reduced. Decreasing the size of the device also reduces the distance between the source and drain, resulting in a phenomenon called Short-Channel Effects (SCEs). In a continuous effort to overcome the problems posed by SCEs, the classical, planar, single-gate MOSFET device has evolved into a three-dimensional device with structural modifications. Increasing the effective number of gates around a channel will enhance the electrostatic control of the channel by the gates and thus reduce the SCEs. In recent times, scaling of MOSFETs has reached the physical limitation of their size (5 nm), and this has raised the need for novel device architectures to replace the MOSFET technology for semiconductor industries.

1.2 VLSI Design Hierarchy

Very-Large-Scale Integration (VLSI) is the method of generating an IC by merging transistors, resistors, or other electronic components in a single chip. VLSI design is used to minimize the size of circuits and cost of devices. It can be achieved by increasing the number of transistors used in ICs.

Figure 1.1 shows the VLSI design hierarchy with different design levels. The VLSI design can be divided into five levels of hierarchy based on the top-down approach. The first level is considered the system level or IC level and is also known as the final outcome of the VLSI design. The second level is known as the module level. IC design is generally divided into different modules. Based on the complexity, the module can again be divided into submodules. This can be carried on till the complexity could be reduced. Below the module level is the gate level. In this hierarchy level, each module or submodule is designed using the basic logic gates. The fourth level of hierarchy occurs at the circuit level. Each logic gate in the gate level is implemented by using transistors at this point of design. The final level is the device level.

FIGURE 1.1 VLSI design hierarchy levels.

The size of transistors used in VLSI design is constantly reduced to provide more functionality, minimize cost, and to speed up the design process. If there is a change in the device level as the size of the transistor gets reduced, obviously the circuit level also changes as per the transistor size. The impact on the circuit level leads to changes in the gate level. The gate level changes have an influence on the module level, and finally it is all reflected in the system level. Thus, the device level plays a highly significant role in VLSI design. The commonly used device for VLSI design is a Metal-Oxide Semiconductor Field Effect Transistor (MOSFET).

1.3 MOSFET Basics

A MOSFET is a frequently used type of transistor with a “Metal Oxide” gate, and this part of the device is electrically sheathed from the channel of the semiconductor. And due to this phenomenon, we can say “NO current flows into the gate”. MOSFETs can generally be classified into two types – depletion mode and enhancement mode, and each of these two types has an n/p channel type.

When no voltage is applied at the source and drain junction, a depletion mode transistor acts much like a switch that is “Normally Closed”. A depletion mode n-channel MOSFET structure is shown in Figure 1.2. A “positive” voltage applied to the gate expands the channel for an n-channel MOSFET, increasing the flow of the current in the drain. Similarly, when the gate is supplied with a “negative” voltage, the drain current is highly reduced as the channel shrinks in size. The same concept is applicable for the devices made of p-channels, too.

FIGURE 1.2 Structure of an n-channel and p-channel depletion MOSFET.

Enhancement devices are normally preferred to depletion mode devices in practical applications. A device is normally in an “ON” condition and a gate source voltage (V_gs) is required to turn the device “OFF”. An enhancement mode n-channel MOSFET structure is shown in Figure 1.3. An electrical field is produced within a channel by applying a positive voltage that decreases the resistance of the channel and allows the electrons to get attracted towards the oxide layer, resulting in channel conduction. As the positive voltage applied to the gate is gradually increased, the drain current is also increased. This concept is acceptable for p-channel enhancement forms too. MOSFETs can generally be used as electronic switches or amplifiers due to their very low power consumption. The four types of ON and OFF states of a MOSFET switch are summarized in Table.1.1.

FIGURE 1.3 Structure of an n-channel and p-channel enhancement MOSFET.

TABLE 1.1
ON and OFF States of MOSFET Types

Device Type	Gate Source Voltage (Vgs)
	Positive	Zero	Negative
P-Depletion MOSFET	OFF	ON	ON
P-Enhancement MOSFET	OFF	OFF	ON
N-Depletion MOSFET	ON	ON	OFF
N-Enhancement MOSFET	ON	OFF	OFF

1.3.1 NMOS Enhancement Mode MOSFET Operation

An N-channel Metal Oxide Semiconductor (NMOS) structure is a better candidate to easily understand the methodology and rules of design and provide a basic introduction to VLSI design. To build a channel for conduction, the minimum voltage known as the threshold voltage must be defined. There are three sets of conditions with respect to drain source voltage (V_ds), gate source voltage (V_gs), and threshold voltage (V_t) to understand the operation of an NMOS transistor operating in enhancement mode.

• When V_gs > V_t and V_ds = 0
  A channel is formed, but there is no current between the source and drain regions as the drain source voltage is zero.
  Id=0(1.1)
• When V_gs > V_t and V_ds < V_gs − V_t
  When applying V_ds, current flows in the channel. Hence, a potential is developed in the region between the gate and the channel, and this potential is found to be varying with the distance across the channel at the source end. Here the maximum voltage is V_gs. The device operates in a non-saturated region ...

Table of contents

• Cover
• Half Title
• Title Page
• Copyright Page
• Table of Contents
• Preface
• Editors
• Contributors
• Chapter 1 MOSFET Design and Its Optimization for Low-Power Applications
• Chapter 2 RF/Analog and Linearity Performance Evaluation of a Step-FinFET under Variation in Temperature
• Chapter 3 Low-Power Memory Design for IoT-Enabled Systems: Part 1
• Chapter 4 Low-Power Memory Design for IoT-Enabled Systems: Part 2
• Chapter 5 Performance Evaluation of a Novel Channel Engineered Junctionless Double-Gate MOSFET for Radiation Sensing and Low-Power Circuit Application
• Chapter 6 Technological Challenges and Solutions to Advanced MOSFETs
• Chapter 7 Energy Storage Device Fundamentals and Technology
• Chapter 8 Energy Storage Devices
• Chapter 9 A Heuristic Approach for Modelling and Control of an Automatic Voltage Regulator (AVR)
• Chapter 10 Reduced-Order Modelling and Control of a Single-Machine Infinite Bus System with the Grey Wolf Optimizer (GWO)
• Chapter 11 Internet of Things (IoT) with Energy Sector-Challenges and Development
• Chapter 12 Automatic and Efficient IoT-Based Electric Vehicles and Their Battery Management System: A Short Survey and Future Directions
• Chapter 13 A Hybrid Approach for Model Order Reduction and Controller Design of Large-Scale Power Systems
• Chapter 14 Day-Ahead Electricity Price Forecasting for Efficient Utility Operation Using Deep Neural Network Approach
• Chapter 15 MEMS Devices and Thin Film-Based Sensor Applications
• Chapter 16 Structural, Optical, and Dielectric Properties of Ba-Modified SrSnO3 for Electrical Device Application
• Chapter 17 Fabrication and Characterization of Nanocrystalline Lead Sulphide (PbS) Thin Films on Fabric for Flexible Photodetector Application
• Chapter 18 Effect of Stiffness in Sensitivity Enhancement of MEMS Force Sensor Using Rectangular Spade Cantilever for Micromanipulation Applications
• Chapter 19 Successive Ionic Layer Adsorption and Reaction Deposited ZnS-ZnO Thin Film Characterization
• Chapter 20 State of Art for Virtual Fabrication of Piezoresistive MEMS Pressure Sensor
• Chapter 21 Role of Aqueous Electrolytes in the Performance of Electrochemical Supercapacitors
• Chapter 22 Graphene for Flexible Electronic Devices
• Chapter 23 Flexible Microfluidics Biosensor Technology
• Index