Multi-Processor System-on-Chip 2

Applications

Liliana Andrade, Frederic Rousseau

• Publisher: Wiley-ISTE
• Year: 2021
• ISBN:
  9781119818403
• Edition: 1
• Topic: Computer Science
• Subtopic: Operating Systems
• Index: Computer Science

A Multi-Processor System-on-Chip (MPSoC) is the key component for complex applications. These applications put huge pressure on memory, communication devices and computing units. This book, presented in two volumes – Architectures and Applications – therefore celebrates the 20th anniversary of MPSoC, an interdisciplinary forum that focuses on multi-core and multi-processor hardware and software systems. It is this interdisciplinarity which has led to MPSoC bringing together experts in these fields from around the world, over the last two decades.

Multi-Processor System-on-Chip 2 covers application-specific MPSoC design, including compilers and architecture exploration. This second volume describes optimization methods, tools to optimize and port specific applications on MPSoC architectures. Details on compilation, power consumption and wireless communication are also presented, as well as examples of modeling frameworks and CAD tools. Explanations of specific platforms for automotive and real-time computing are also included.

PART 1
MPSoC for Telecom

1
From Challenges to Hardware Requirements for Wireless Communications Reaching 6G

Stefan A. DAMJANCEVIC¹, Emil MATUS¹, Dmitry UTYANSKY², Pieter VAN DER WOLF³ and Gerhard P. FETTWEIS¹, ⁴

¹ Vodafone Chair Mobile, Communications Systems, TU Dresden, Germany

² Synopsys, Saint Petersburg, Russia

³ Solutions Group, Synopsys, Inc., Eindhoven, The Netherlands

⁴ Barkhausen Institut, TU Dresden, Germany

Over the past few decades, we have seen rapid innovation in wireless communications. In particular, the IEEE 802.11 and 3GPP standardization organizations have driven data rates into the Gb/s range, enabling modern life, at home, at work and on the road. Societies of today have become dependent on this important infrastructure. The basis of this development is an infrastructure based on electronic circuits, which are driven, at heart, by very advanced multi-processor system-on-chip engines.

Firstly, we want to deliver a vision on what is to be expected from 6G, the next innovation wave of cellular technology. Cellular 1G was about delivering analogue voices, and digital 2G fixed it. The intention of 3G was to deliver data, but only 4G made it proficiently available for the service requirements. With 5G, we see the advent of the Tactile Internet, i.e. connecting remote controls not as point-to-point solutions but via a network. Will 6G be just a “fix” of issues left unsolved? We believe 6G will deliver truly more than this, and will also require many more sophisticated signal processing tasks.

Secondly, we want to analyze the computational tasks of 5G and beyond baseband processing, as well as their specification requirements. It becomes clear that the heterogeneity of computation cannot be mapped efficiently onto a homogeneous processor array. Instead, we need to find the right architecture for the right task. The reader is introduced to an extremely varied set of requirements as the services dramatically differ in terms of latency, data rate and reliability.

Thirdly, we want to give perspective and a sense of scale required from hardware for the previously determined corner workloads. We do this by implementing an example beyond 5G algorithm generalized frequency division multiplexing, with regard to those workloads, on a prototype software programmable single-instruction, multiple-data wide vector processing machine. Workloads alone are not sufficient to deduce adequate requirements for hardware (HW). To bridge the gap between workloads and HW requirements, we need to know how the 6G candidate waveform modulation translates workloads into HW requirements.

Conclusively, the performance–cost analysis shows a need for high flexibility. The low-end use case of the implemented algorithm easily fits within one 1 GHz 512 bit vector processor core requiring 1.01 − 5.39 MHz of the processor clock budget, therefore enabling seamless time multiplexing with other software (SW) kernels running on the core. The carrier aggregation (CA) high-end use case requires 921 − 5,505 MHz, which allows the prior clock-efficient version to fit on one 1 GHz 512 bit vector processor core. This sets the stage for the system designer to opt between a generalized vector processor or some more specialized HW accelerator engine, such as a dedicated (application-specific) HW accelerator or an application-specific instruction set processor (ASIP). Finally, the implemented algorithm running the multiple-input, multiple-output (MIMO) CA high-end use case would require a budget of 7.37 − 44.04 GHz, the theoretical equivalent of eight or forty-five 512 bit vector processor cores, making the high-end use case more suitable for execution on the dedicated HW accelerator or the ASIP, which were otherwise powered down. The use case corners demonstrate a high variability requirement from HW, which makes heterogeneous multi-processor system-on-chip (MPSoC) solutions ideal future-proof HW for beyond 5G. In this chapter, we present our key findings that connect the dots from vision to future HW in wireless communications.

1.1. Introduction

As we are writing this chapter in early 2020, it is obvious that there exists a gap between the conventional 5G vision (Fettweis 2012; NGMN Alliance 2015; Qualcomm 2016) and the deployed 5G. We do not have coordinated unmanned areal vehicles (UAV) groups humming over our cities like busy worker bees around hives (ARIB et al. 2016). We do not have critical vehicle to everything (V2X) communication with 1 ms end-to-end latency coordinated “emergency trajectory adjustment” (3GPP 2018d) keeping us safe, nor the smart infrastructure that would make traffic lights obsolete (Fettweis 20...