Semiconductor Devices and Technologies for Future Ultra Low Power Electronics

D. Nirmal, J. Ajayan, Patrick J. Fay, D. Nirmal, J. Ajayan, Patrick J. Fay

• Publisher: CRC Press
• Year: 2021
• Print ISBN: 9781032061610
• eBook ISBN: 9781000475364
• Topic: Technology & Engineering
• Subtopic: Electrical Engineering & Telecommunications
• Index: Technology & Engineering

This book covers the fundamentals and significance of 2-D materials and related semiconductor transistor technologies for the next-generation ultra low power applications. It provides comprehensive coverage on advanced low power transistors such as NCFETs, FinFETs, TFETs, and flexible transistors for future ultra low power applications owing to their better subthreshold swing and scalability. In addition, the text examines the use of field-effect transistors for biosensing applications and covers design considerations and compact modeling of advanced low power transistors such as NCFETs, FinFETs, and TFETs. TCAD simulation examples are also provided.

FEATURES

• Discusses the latest updates in the field of ultra low power semiconductor transistors
• Provides both experimental and analytical solutions for TFETs and NCFETs
• Presents synthesis and fabrication processes for FinFETs
• Reviews details on 2-D materials and 2-D transistors
• Explores the application of FETs for biosensing in the healthcare field

This book is aimed at researchers, professionals, and graduate students in electrical engineering, electronics and communication engineering, electron devices, nanoelectronics and nanotechnology, microelectronics, and solid-state circuits.

1An Introduction to Nanoscale CMOS Technology Transistors

A Future Perspective

Kumar Prasannajit Pradhan

DOI: 10.1201/9781003200987-1

CONTENTS

1.1Introduction: Background and Driving Forces

1.2The Era of Nanoelectronics

1.3ITRS Technology Targets

1.3.1High Performance (HP)

1.3.2Low Power (LP)

1.3.3Low Standby Power (LSTP)

1.4Issues due to the Miniaturization of Devices

1.5Historical Survey

1.6FinFETs: Pros, Cons, and Possible Alternatives

1.6.1FinFETs from an Industry Aspect

1.6.2FinFETs: A Journey

1.6.3Ultra-Thin Body Devices

1.6.4Multi-Gate MOSFETs

1.6.5Hybrid FinFETs

1.7Device Performance and Reliability Metrics

1.7.1Static Performance

1.7.2Switching Parameters

1.7.3Intrinsic Delay

1.7.4Analog and RF Performance

1.7.5Analog Performance

1.7.6RF Performance

1.7.7Reliability Aspects

1.8Devices in the Race for Future Technology

References

1.1INTRODUCTION: BACKGROUND AND DRIVING FORCES

There is a great demand for electronic gadgets as space, consumer, and defense industries, and the most recent evolution of artificial intelligence and Internet of Things (IoT) era have created the opportunity for further research in this field. The main driving power to make everything possible is the innovation of semiconductor transistors such as metal oxide semiconductor field-effect transistors (MOSFETs) and integrated circuits (ICs). The worldwide popularity of the transistors has helped create multimillion semiconductor industries with continued progress. To assimilate more functions and fulfill significant demands, the IC industries continuously focused on achieving high performance with low-cost devices through large-volume production. As the MOSFETs are the unit component of ICs, the main focus is on establishing new transistors that are faster in performance and smaller in size than their predecessors. And the ultimate concern regarding the novel transistors is that they should support a high grade of reliability with low cost. Hence, accomplishing these critical goals is the primary driving force in further exploring a comprehensive transistor research in academia and industry.

The journey started with the invention of first point-contact field-effect transistor by John Bardeen, William Shockley, and Walter Brattain in 1947 [1]. Hereafter, there has been irrepressible advancement after the announcement of Kahng and Atalla in 1960 regarding the very first invention of MOSFET [2].

Further, in 1965, Gordon E. Moore, cofounder of the Intel Corporation, formulated a law popularly known as Moore’s law. The law affirms that “The number of transistors incorporated in a chip will approximately double in every 24 months” [3] and after that, it is widely accepted by the semiconductor industries. According to the predictions, the miniaturization in transistor size with increasing package density will be continued, which enables the present-day innovations in the era of electronics. A basic understanding of Moore’s law is shown in Figure 1.1.

In the continued effort to miniaturize or make the transistors small, the dimensions have become the primary bottleneck for further improvement in the device performance. Along the endless innovations in the fabrication processes, the semiconductor foundries (as ST-Microelectronics, TSMC, Intel, SMIC, CEA-Leti, Global Foundries, etc.) have entered from bulk to nano electronics era. Figure 1.2 (a) demonstrates the primary requirement of technology improvement to accomplish the market demand. The constant progress in semiconductor processing has made it possible to move beyond “Moore’s Law,” that is, “More Moore” and “More-Than-Moore (MtM)” with state-of-the-art IC chips (beyond CMOS technology) containing more than a billion transistors.

The International Technology Roadmap for Semiconductors (ITRS) [4] is giving the 15-year assessment predictions of the semiconductor industry’s future technological requirements. The ITRS predictions have assisted in creating opportunities for research and development (R&D) and academia to come up with strategic outcomes for fulfilling the requirements of future demands. The Executive Summary of the ITRS furnish a taxonomy of scaling in the classical “More Moore” and “MtM” sense as shown in Figure 1.2 (b).

Moreover, the “More Moore” describes the three types of scaling approaches:

• Geometrical (constant field scaling): shrinking of horizontal and vertical physical feature sizes of the devices to improve density, performance, and reliability.
• 3-D devices, modification of nongeometrical process techniques and new materials that affect the electrical performance of the chip.
• It enables HP, LP, reliability, and low-cost productivity. Specific design technologies that address the power and performance trade-offs associated with functionality needs.

FIGURE 1.1Basic Understanding of Moore’s Law

And finally, the functional diversification of the MtM approach typically admits for the non-digital functionalities (e.g., power control, analog and RF communication, passive components, actuators, sensors, etc.) to migrate from the system board-level to an exact package-level like system-in-package (SiP) or system-on-a-chip (SoC) for potential solutions. The aspiration to integrate additional functionality into the ICs results in an endless race of shrinking the device dimensions. The benefits of scaling are higher packaging density with a high switching speed and low power dissipation.

In the history of electronics era, all the emerging innovations have been feasible due to the strong association among the devices and materials research. Primarily, the market demand for three different kinds of application-oriented ICs as low power (LP), high performance (HP), and low standby power (LSTP) became a major challenge to fulfill the demand for the CMOS technology of sub 50 nm gate length [5]. To overcome the challenges that appeared in miniaturizing, the ITRS offers diverse approaches leading to nonclassical CMOS technology. The next two approaches are extensively explored and widely adopted by many leading industries:

FIGURE 1.2(a) The Requirement of Technology Innovation in a Cyclic Process and (b) Demand to Shift beyond CMOS Technology [4]

1. The structural modifications leading to novel transistor architectures with enhanced electrostatic performance.
2. The evolution of new materials with better carrier transport efficiency.

As semiconductor designs become progressively complex with the devices getting smaller and smaller, the optimization of the structures becomes a hurdle for the designers. Also, the semiconductor manufacturers face the challenge of establishing process technologies within the cost constraints and stipulated time frame. The number of wafers required to implement the new process is one key factor for deciding the cost and time. Hence, modeling and Technology CAD (Computer Aided Design, or TCAD) simulation become the computing paradigm prior...

Table of contents

• Cover
• Half Title Page
• Title Page
• Copyright Page
• Contents
• Preface
• Editors
• Contributors
• Chapter 1 An Introduction to Nanoscale CMOS Technology Transistors: A Future Perspective
• Chapter 2 High-Performance Tunnel Field-Effect Transistors (TFETs) for Future Low Power Applications
• Chapter 3 Ultra Low Power III-V Tunnel Field-Effect Transistors
• Chapter 4 Performance Analysis of Carbon Nanotube and Graphene Tunnel Field-Effect Transistors
• Chapter 5 Characterization of Silicon FinFETs under Nanoscale Dimensions
• Chapter 6 Germanium or SiGe FinFETs for Enhanced Performance in Low Power Applications
• Chapter 7 Switching Performance Analysis of III-V FinFETs
• Chapter 8 Negative Capacitance Field-Effect Transistors to Address the Fundamental Limitations in Technology Scaling
• Chapter 9 Recent Trends in Compact Modeling of Negative Capacitance Field-Effect Transistors
• Chapter 10 Fundamentals of 2-D Materials
• Chapter 11 Two-Dimensional Transition Metal Dichalcogenide (TMD) Materials in Field-Effect Transistor (FET) Devices for Low Power Applications
• Index