Energy Efficient and Reliable Embedded Nanoscale SRAM Design

Bhupendra Singh Reniwal, Pooran Singh, Ambika Prasad Shah, Santosh Kumar Vishvakarma

• Publisher: CRC Press
• Year: 2023
• Print ISBN: 9781032081595
• eBook ISBN: 9781000985153
• Edition: 1
• Topic: Technology & Engineering
• Subtopic: Electrical Engineering & Telecommunications
• Index: Technology & Engineering

This reference text covers a wide spectrum for designing robust embedded memory and peripheral circuitry. It will serve as a useful text for senior undergraduate and graduate students and professionals in areas including electronics and communications engineering, electrical engineering, mechanical engineering, and aerospace engineering.

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• Discusses low-power design methodologies for static random-access memory (SRAM)

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• Covers radiation-hardened SRAM design for aerospace applications

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• Focuses on various reliability issues that are faced by submicron technologies

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• Exhibits more stable memory topologies

Nanoscale technologies unveiled significant challenges to the design of energy- efficient and reliable SRAMs. This reference text investigates the impact of process variation, leakage, aging, soft errors and related reliability issues in embedded memory and periphery circuitry.

The text adopts a unique way to explain the SRAM bitcell, array design, and analysis of its design parameters to meet the sub-nano-regime challenges for complementary metal-oxide semiconductor devices. It comprehensively covers low- power-design methodologies for SRAM, exhibits more stable memory topologies, and radiation-hardened SRAM design for aerospace applications. Every chapter includes a glossary, highlights, a question bank, and problems. The text will serve as a useful text for senior undergraduate students, graduate students, and professionals in areas including electronics and communications engineering, electrical engineering, mechanical engineering, and aerospace engineering. Discussing comprehensive studies of variability-induced failure mechanism in sense amplifiers and power, delay, and read yield trade-offs, this reference text will serve as a useful text for senior undergraduate, graduate students, and professionals in areas including electronics and communications engineering, electrical engineering, mechanical engineering, and aerospace engineering. It covers the development of robust SRAMs, well suited for low-power multi-core processors for wireless sensors node, battery-operated portable devices, personal health care assistants, and smart Internet of Things applications.

Table of contents

• Cover
• Half Title
• Title
• Copyright
• Contents
• Acknowledgment
• Preface
• Author Bios
• Chapter 1 Introduction
• Chapter 2 Design Metrics for Embedded SRAM
• Chapter 3 SRAM Bitcells over Conventional Memories
• Chapter 4 Offset Correction in the Sense Amplifier
• Chapter 5 Data Sensing in SRAM: A Hybrid Approach with FinFET
• Chapter 6 BTI-Aware and Soft-Error-Tolerant SRAM
• Index