Short channel GaN FET MMIC technology for high reliability applications

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• Publisher: Cuvillier Verlag
• Year: 2024
• Print ISBN: 9783736979567
• eBook ISBN: 9783736969568
• Edition: 1

Nowdays GaN HEMT technology reached maturity level that allows industral fabrication of such devices for wide range of civil (telecommunications, power electrinics, automotive etc.), as well as space and military (phased array radars) applications. At this level, technology start reaching physical limits of GaN material and require new approaches that will allow to overcome some of well known problems related to GaN HEMTs, such as high gate leakage currents, reliability issues and difficulties of normally-off transistor fabrication. The goal of these theses is theoretical and experimental confirmation of the idea, that using peizoelectric nature of GaN crystal will allow local modification of GaN HEMT channel by means of external mechanical stress (using first and second passivation layers as stressors). After implementation of the proposed technology changes and new device geometry in process flow intended for 150 nm GaN HEMT MMIC fabrication, E/D devices with pinch-off voltages +0.1V and -1.65V respectively were fabricated on the same wafer within single process flow. It was observed, that E-mode devices, fabricated using compressed passivation layers, demonstrate lower gate leakage currents and more robust in HTRB test as compared to D-mode devices.In summary, it was demonstrated, that it is possible to control pinch-off voltage and gate leakage current of short channel GaN HEMTs by application of external stress. Usage of external stress, opens new degree of freedom in device optimization, and extends opportunities for more advanced MMIC design.

Table of contents

• Zusammenfassung
• Abstract
• Table of Contents
• List of abbreviations
• 1 Introduction
• 1.1 High reliability applications and potential of GaN in thisarea
• 1.2 Current state of K- and Ka-band GaN FET technology
• 1.3 Full cycle of GaN MMIC development and testing
• 2 Main challenges of scaling down gate dimensionsin GaN FETs
• 2.1 Short channel effects and limitations on epitaxialstructure
• 2.2 Challenges in reducing parasitic effects limiting highfrequencyperformance GaN FETs
• 2.3 Difficulties in physical modeling of short channel GaNHEMTs
• 3 Development and optimization of technologicalprocess flow for 100 nm GaN MMICs
• 3.1 Basic process flow for embedded gate fabrication
• 3.2 Concept of novel gate approach
• 3.3 Development of process for shallow gate trenchfabrication
• 3.4 Sputtered Ir metal deposition process
• 3.5 Development of process for Ir etching
• 3.6 Optimization of ohmic contact formation process
• 3.7 Optimization of gate shape for gate capacitance reduction
• 3.8 Creation of models for developed processes
• 4 Extension of sputtered Ir approach to Ir – plugtechnology
• 4.1 Potential problems associated with embedded T-gates
• 4.2 Extension of the developed processes for creation of theIr plug
• 4.3 Stress calculation in different gate constructions
• 5 Electrical performance comparison of transistorswith different gate design and Al composition inbarrier layer
• 5.1 DC performance
• 5.2 Dynamic performance
• 5.3 Small-signal performance
• 5.4 Large-signal performance
• 5.5 Reliability screening tests results
• 6 Strain engineering of AlGaN/GaN HEMTs
• 6.1 Polar properties of wurtzite GaN and AlGaN
• 6.2 Mechanical strain in the AlGaN/GaN HEMTs
• 6.3 External mechanical strain influence on the electricalperformance of AlGaN/GaN HEMTs
• 6.4 Factors affecting local strain of AlGaN layer in the trench
• 6.5 Possible applications of trench strain engineering forAlGaN/GaN MMIC fabrication
• 7 Conclusions
• 8 References