- 124 pages
- English
- PDF
- Available on iOS & Android
About this book
GaAs-based 9xx-nm broad-area diode lasers (BALs) offer the highest optical power (Popt) among diode lasers and the highest conversion efficiency (?E) among all light sources. Therefore, they are widely used in material processing applications (e.g. metal cutting), which additionally require high beam quality (i.e. low beam parameter product BPP), typically limited in BALs along the lateral axis (BPPlat). Enhancing BAL performance is dependent on identifying the thermal and non-thermal limiting mechanisms, and implementing design changes to minimize their effects. In this work, two novel approaches based on lateral structuring are developed, aiming to overcome different limiting mechanisms acting along the lateral axis. First, the enhanced self-aligned lateral structure (eSAS) is based on integrating structured current-blocking layers outside the BAL stripe to centrally confine current and charge carriers, thereby suppressing lateral current spreading and lateral carrier accumulation. Two eSAS variants are optimized using simulation tools, then realized in multiple wafer processes, followed by characterization of mounted BALs. eSAS BALs exhibit state-of-the-art Popt and lateral brightness (Popt/BPPlat), with clear benefits over standard gain-guided BALs in terms of threshold, BPPlat and peak ?E. The second approach is chip-internal thermal path engineering, based on structured epitaxial layers replaced outside the stripe by heat-blocking materials to centrally confine heat flow. This flattens the lateral temperature profile (i.e. reduces thermal lensing) around the active zone, which is associated with enhanced brightness. Finite-element thermal simulations are used to estimate the benefits of this approach, thereby motivating its practical realization in future studies.
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Table of contents
- Abstract
- Kurzfassung
- List of Publications
- Acknowledgements
- 1Introduction
- 1.1 High-power GaAs-based broad-area diode lasers
- 1.2 Scope and structure of this work
- 2Research Methods and Techniques
- 2.1 Device modeling and simulation tools
- 2.2 Device fabrication technology
- 2.3 Characterization techniques and measurement setups
- 3Literature Review
- 3.1 Performance of state-of-the-art devices
- 3.2 Limiting factors to device performance
- 3.3 Previous lateral design approaches: benefits and limitations
- 4Enhanced Self-Aligned Lateral Structure(eSAS)
- 4.1 Device design and simulation results
- 4.2 eSAS first variant (V1): realization and quality control
- 4.3 eSAS second variant (V2): realization and quality control
- 4.4 Device characterization and measurement results
- 4.5 Overview and outlook
- 5Chip-Internal Thermal Path Engineering:Design and Outlook
- 5.1 Motivation and prior art
- 5.2 Thermal simulation model
- 5.3 Thermal simulation results and analysis
- 6Summary and Conclusion
- List of Figures
- List of Tables
- Symbols and Acronyms
- References