
- 470 pages
- English
- ePUB (mobile friendly)
- Available on iOS & Android
Advanced Routing of Electronic Modules
About this book
The rapid growth of the electronic products market has created an increasing need for affordable, reliable, high-speed and high-density multi-layer printed circuit boards (PCBs). This book presents the technologies, algorithms, and methodologies for engineers and others developing the next generation of electronic products.
A vision of the future in advanced electronics
Advanced Routing of Electronic Modules provides both fundamental theory and advanced technologies for improving routing. Beginning chapters discuss approaches to approximate a minimum rectilinear Steiner tree from a minimum spanning tree and introduce ways to avoid obstacles for routing simple multi-terminal nets sequentially in a workspace. Timing delay, clock skew, and noise control requirements in signal integrity are described as well as computer-aided approaches to managing these requirements in high-speed PCB/MCM routing.
Later chapters present the two-layer wiring problem, rip-up and reroute approaches, and parallel routing, including global routing, boundary crossing placement, and detailed maze routing in hardware acceleration. Data structures, data management, and algorithms for parallel routing in a multiple-processor hardware systems are also covered.
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Information
Table of contents
- Cover
- Half Title
- Title Page
- Copyright Page
- Preface
- Table of Contents
- Contributors
- Dedication
- Chapter 1: Refinement Approaches for Rectilinear Steiner Tree Construction
- Chapter 2: Rectilinear Interconnections in the Presence of Obstacles
- Chapter 3: The General Solution of the Rectilinear Steiner’s Problem and Its Applications
- Chapter 4: Performance-Driven Global Routing and Wiring Rule Generation for High-Speed PCBs and MCMs
- Chapter 5: Routing for Analog and Mixed Circuits
- Chapter 6: Segmented Channel Routing
- Chapter 7: Restricted Routing for CMOS Gate Arrays
- Chapter 8: Recent Developments in Wiring and Via Minimization
- Chapter 9: Layout Compaction for High-Performance/Large-Scale Circuits
- Chapter 10: Rip-Up and Reroute Strategies
- Chapter 11: Parallel Routing
- Appendix A: Symbols
- Appendix B: Acronyms
- Appendix C: Glossary
- Index