Layout Techniques for Integrated Circuit Designers
eBook - PDF

Layout Techniques for Integrated Circuit Designers

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  1. 463 pages
  2. English
  3. PDF
  4. Available on iOS & Android
eBook - PDF

Layout Techniques for Integrated Circuit Designers

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About this book

This book provides complete step-by-step guidance on the physical implementation of modern integrated circuits, showing you their limitations and guiding you through their common remedies. The book describes today's manufacturing techniques and how they impact design rules. You will understand how to build common high frequency devices such as inductors, capacitors and T-coils, and will also learn strategies for dealing with high-speed routing both on package level and on-chip applications. Numerous algorithms implemented in Python are provided to guide you through how extraction, netlist comparison and design rule checkers can be built. The book also helps you unravel complexities that effect circuit design, including signal integrity, matching, IR drop, parasitic impedance and more, saving you time in addressing these effects directly. You will also find detailed descriptions of software tools used to analyze a layout database, showing you how devices can be recognized and connectivity accurately assessed. The book removes much of fog that often hides the inner workings of layout related software tools and helps you better understand: the physics of advanced nodes, high speed techniques used in modern integrated technologies, and the inner working of software used to analyze layout databases. This is an excellent resource for circuit designers implementing a schematic in a layout database, especially those involved in deep submicron designs, as well as layout designers wishing to deepen their understanding of modern layout rules.

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Table of contents

  1. Layout Techniques for Integrated Circuit Designers
  2. Contents
  3. Preface
  4. Chapter 1 Introduction
  5. Part I: Manufacturing and Physical Layout Techniques
  6. Chapter 2 Preliminaries
  7. Chapter 3 Device Formation in Layout
  8. Chapter 4 Layout with Ultrasmall Geometry CMOS Technologies
  9. Chapter 5 Layout with Bipolar Technologies SiGe
  10. Chapter 6 Aspects of High-Speed Layout 10–100+ GHz
  11. Part II: Layout Verification Techniques
  12. Chapter 7 Extraction Techniques
  13. Chapter 8 Netlist Comparators
  14. Chapter 9 Design Rule Checkers
  15. 9.1 Implementations of Design Rules
  16. 9.2 Summary
  17. Exercies
  18. References
  19. Acronyms and Abbreviations
  20. Index