Low Power VLSI Design

Fundamentals

Angsuman Sarkar, Swapnadip De, Manash Chanda, Chandan Kumar Sarkar

• Publisher: De Gruyter Oldenbourg
• Year: 2016
• eBook ISBN: 9783110455458
• Edition: 1
• Topic: Technology & Engineering
• Subtopic: Electrical Engineering & Telecommunications
• Index: Technology & Engineering

This book teaches basic and advanced concepts, new methodologies and recent developments in VLSI technology with a focus on low power design. It provides insight on how to use Tanner Spice, Cadence tools, Xilinx tools, VHDL programming and Synopsis to design simple and complex circuits using latest state-of-the art technologies. Emphasis is placed on fundamental transistor circuit-level design concepts.

1Introduction to Low Power Issues in VLSI

1.1Introduction to VLSI

This chapter gives a brief description of low power digital and analog very-large-scale integration (VLSI) design. It is also treated as a review of basic principles rather than an in-depth treatment of individual advanced topics.

Over the last two decades, “wireless communication” is considered as one of the major successes of engineering, not only due to its huge technological growth, but also due to its societal and economic impact. The evolution of wireless communication is directly linked to power consumption of the devices. The gap between small-sized battery capacity and power requirement has become a critical factor to be considered for most hand-held portable wireless devices. Thus, energy efficiency and low power design has become one of the most important topics in integrated circuit (IC) design.

The chief design goal of today’s ICs can be listed as higher speed, higher accuracy and reliability and low power drain. In the design of high performance analog/ digital complementary metal oxide semiconductor (CMOS) circuits, energy efficiency plays a crucial role. It has become highly difficult to maintain energy efficiency in medium-to high accuracy circuits with highly scaled CMOS deep-submicron technologies. One of the important purposes of this book is to emphasize some of the important challenges faced by the circuit designers working with aggressively scaled devices and reviews of the state-of-the-art device/circuit-level techniques that can be employed to mitigate those challenges.

The CMOS digital ICs play a very important role in technology for modern information age. Because of their intrinsic features in low power consumption, large noise margins and ease of design, CMOS ICs have been widely used to develop random access memory (RAM) chips, microprocessor chips, digital signal processor chips and application-specific integrated circuit (ASIC) chips. The popular use of CMOS circuits continues to grow with the increasing demands for low power, low noise integrated electronic systems in the development of portable computers, portable phones and multimedia agents.

As more and more complex functions are required in various data processing and telecommunication devices, the need to integrate these functions in a small package is also increasing (International Technology Roadmap for Semiconductors, http://public.itrs.net, 2009). The level of integration is measured in terms of number of logic gates in chip. So the number of logic gates is also increasing. These advances in device manufacturing technology allow steady reduction of minimum feature size as well as channel length and power consumption per function. This also increases the speed of the device.

As process technology scales beyond 100 nm feature sizes, for functional and high-yielding silicon, the traditional design approach needs to be modified to cope with interconnect processing difficulties and other newly exacerbated physical effects. The scaling of gate oxide in the nano-CMOS regime results in a significant increase in gate direct tunneling current [1]. The effect of gate-induced drain leakage (GIDL) is felt in designs, such as DRAM and low power SRAM, where the gate voltage is driven negative with respect to the source. If these effects are not taken care of, the result will be a nonfunctional SRAM, DRAM or any other circuit that uses this technique to reduce subthreshold leakage [2].

The level of integration as measured by the number of logic gates in monolithic chip is increasing over the past three decades, mainly due to the rapid progress in process technology and interconnects technology.

–Multifunctional chips (1962) contain 2–4 logic blocks per chip.

–MSI (medium-scale integration) (1967) chips contain 20–200 logic blocks per chip.

–LSI (large-scale integration) chips contain 200–2,000 logic blocks per chip.

–VLSI (very-large-scale integration) chips contain 2,000–20,000 logic blocks per chip.

–ULSI (ultralarge-scale integration) chips contain >20,000 logic blocks per chip.

As the technology scales down with its pace determined by famous Moore’s law, the supply voltage needs to be scaled down along with the transistor dimensions. This is primarily due to the fact that decreasing supply voltage helps to avoid possible breakdown of MOS transistors with ultrathin gate oxides. In an inverter cell, considered as the simplest logic gate, estimated power consumption can be expressed as

where CL designates the load capacitor to be driven, VDD is the supply voltage and f is the frequency of operation.

Therefore, if speed has to be increased, simultaneous reduction of power consumption is also necessary. Supply voltage reduction can be employed as an efficient tool to achieve it. In general, to provide sufficient lifetime to the digital circuitry and to keep power consumption at an acceptable level, downscaling is accompanied by supply voltage reduction [3–5]. It is worth mentioning that this evolution is true for digital domain, not the analog domain.

1.2Low Power IC Design beyond Sub-20 nm Technology

Sub-20 nm process technology promises boost in performance, capacity breakthrough and significant power reduction. However, they possess several challenges to the IC design and manufacturing, requiring changes ranging from custom cell design to system-on-chip (SoC) integration. The cost of sub-20 nm is not cheap. However, despite their cost, with its power, performance and area gains (PPA), sub-20 nm process technology promises a new generation of smaller, faster and cheaper product in areas such as mobile computing, smartphones, servers, entertainment and wireless equipment. Although the projected improvements of sub-20 nm technologies are compelling, the challenges and requirements are also extremely large. The challenges and requirements for adaptation of sub-20 nm technology are shown in Figure 1.1.

Figure 1.1: Challenges and requirements of sub-20 nm technology adaptation.

1.3Issues Related to Silicon Manufacturability and Vari...

Table of contents

• Cover
• Title Page
• Copyright
• Dedication
• Preface
• Contents
• 1 Introduction to Low Power Issues in VLSI
• 2 Scaling and Short Channel Effects in MOSFET
• 3 Advanced Energy-reduced CMOS Inverter Design
• 4 Advanced Combinational Circuit Design
• 5 Advanced Energy-reduced Sequential Circuit Design
• 6 Introduction to Memory Design
• 7 Analog Low Power VLSI Circuit Design
• Index