Encyclopedia Of Thermal Packaging, Set 2: Thermal Packaging Tools (A 4-volume Set)

Set 2: Thermal Packaging Tools(A 4–Volume Set)

Avram Bar-Cohen

• Publisher: WSPC
• Year: 2014
• eBook ISBN: 9789814520249
• Topic: Sciences biologiques
• Subtopic: Science générale

Please click here for information on Set 1: Thermal Packaging Techniques

Thermal and mechanical packaging — the enabling technologies for the physical implementation of electronic systems — are responsible for much of the progress in miniaturization, reliability, and functional density achieved by electronic, microelectronic, and nanoelectronic products during the past 50 years. The inherent inefficiency of electronic devices and their sensitivity to heat have placed thermal packaging on the critical path of nearly every product development effort in traditional, as well as emerging, electronic product categories.

Successful thermal packaging is the key differentiator in electronic products, as diverse as supercomputers and cell phones, and continues to be of pivotal importance in the refinement of traditional products and in the development of products for new applications. The Encyclopedia of Thermal Packaging, compiled in four multi-volume sets ( Set 1: Thermal Packaging Techniques, Set 2: Thermal Packaging Tools, Set 3: Thermal Packaging Applications, and Set 4: Thermal Packaging Configurations ) will provide a comprehensive, one-stop treatment of the techniques, tools, applications, and configurations of electronic thermal packaging. Each of the author-written sets presents the accumulated wisdom and shared perspectives of a few luminaries in the thermal management of electronics.

Set 2: Thermal Packaging Tools

The second set in the encyclopedia, Thermal Packaging Tools, includes volumes dedicated to thermal design of data centers, techniques and models for the design and optimization of heat sinks, the development and use of reduced-order “compact” thermal models of electronic components, a database of critical material thermal properties, and a comprehensive exploration of thermally-informed electronic design. The numerical and analytical techniques described in these volumes are among the primary tools used by thermal packaging practitioners and researchers to accelerate product and system development and achieve “correct by design” thermal packaging solutions.

The four sets in the Encyclopedia of Thermal Packaging will provide the novice and student with a complete reference for a quick ascent on the thermal packaging “learning curve,” the practitioner with a validated set of techniques and tools to face every challenge, and researchers with a clear definition of the state-of-the-art and emerging needs to guide their future efforts. This encyclopedia will, thus, be of great interest to packaging engineers, electronic product development engineers, and product managers, as well as to researchers in thermal management of electronic and photonic components and systems, and most beneficial to undergraduate and graduate students studying mechanical, electrical, and electronic engineering.

Foreword
Foreword (English) (42 KB)
Foreword (Japanese) (342 KB)

Please click here for information on Set 1: Thermal Packaging Techniques

Thermal and mechanical packaging — the enabling technologies for the physical implementation of electronic systems — are responsible for much of the progress in miniaturization, reliability, and functional density achieved by electronic, microelectronic, and nanoelectronic products during the past 50 years. The inherent inefficiency of electronic devices and their sensitivity to heat have placed thermal packaging on the critical path of nearly every product development effort in traditional, as well as emerging, electronic product categories.

Successful thermal packaging is the key differentiator in electronic products, as diverse as supercomputers and cell phones, and continues to be of pivotal importance in the refinement of traditional products and in the development of products for new applications. The Encyclopedia of Thermal Packaging, compiled in four multi-volume sets ( Set 1: Thermal Packaging Techniques, Set 2: Thermal Packaging Tools, Set 3: Thermal Packaging Applications, and Set 4: Thermal Packaging Configurations ) will provide a comprehensive, one-stop treatment of the techniques, tools, applications, and configurations of electronic thermal packaging. Each of the author-written sets presents the accumulated wisdom and shared perspectives of a few luminaries in the thermal management of electronics.

Set 2: Thermal Packaging Tools

The second set in the encyclopedia, Thermal Packaging Tools, includes volumes dedicated to thermal design of data centers, techniques and models for the design and optimization of heat sinks, the development and use of reduced-order “compact” thermal models of electronic components, a database of critical material thermal properties, and a comprehensive exploration of thermally-informed electronic design. The numerical and analytical techniques described in these volumes are among the primary tools used by thermal packaging practitioners and researchers to accelerate product and system development and achieve “correct by design” thermal packaging solutions.

The four sets in the Encyclopedia of Thermal Packaging will provide the novice and student with a complete reference for a quick ascent on the thermal packaging “learning curve,” the practitioner with a validated set of techniques and tools to face every challenge, and researchers with a clear definition of the state-of-the-art and emerging needs to guide their future efforts. This encyclopedia will, thus, be of great interest to packaging engineers, electronic product development engineers, and product managers, as well as to researchers in thermal management of electronic and photonic components and systems, and most beneficial to undergraduate and graduate students studying mechanical, electrical, and electronic engineering.

Foreword
Foreword (English) (42 KB)
Foreword (Japanese) (342 KB)

Readership: Packaging engineers, electronic product development engineers, and product managers, as well as researchers in thermal management of electronic and photonic components and systems, and most beneficial to undergraduate and graduate students studying mechanical, electrical, and electronic engineering. Key Features:

Chapter 1

A Review of Cooling Road Maps for 3D Chip Packages

Dereje Agonafer

Jenkins Garrett Professor
Site Director, NSF IUCRC Center in Energy Efficient Systems
Director, Electronics, MEMS & Nanoelectronics Systems Packaging Center
University of Texas at Arlington, U.S.A.
[email protected]

The microelectronics industry has thrived through dimensional scaling and corresponding reduction in cost and increase in performance. It has been reported that the average selling price of a transistor has reduced from a few dollars in the early 50’s to a billionth of a dollar in the early 2000. It has, however, become more difficult to sustain reduction in cost by scaling. Also, while new technology nodes results in reduced gate delay, it also effects an increase in the interconnect delay. One approach to delaying new technology node and improving performance is through reduction in interconnect delay through packaging. In particular, 3-D Through-Silicon-Via (3D TSV) technology is emerging as a powerful technology to reduce package footprint, decrease interconnection power, higher frequencies, and provide efficient integration of heterogeneous devices. TSVs provide high speed signal propagation due to reduced interconnect lengths as compared to wire-bonding and SOC (system-on-chip). However, with many advantages of 3D ICs over conventional 2D counterpart, there are some inherent thermal-mechanical-electrical challenges that need to be addressed before 3D ICs could become mainstream. This chapter talks about a few of the 3D TSV IC challenges from the thermal, mechanical and the performance standpoint of view. It also discusses a novel technique for high powered 3D IC cooling to sub-ambient temperatures using thermo-electric cooler (TEC).

Contents

1.1. Introduction

1.2. TSV Fabrication

1.3. Thermal-Mechanical-Electrical Challenges in 3-D

References

1.1. Introduction

The convergence and miniaturization of computing and communications dictates building up rather than out. As the consumers demand more functions on their hand-held electronic devices, the need for more devices such as memory, CPU and GPU in hand-held type footprints is increasing. This results in high package density. Chip-stacking (3-D) is emerging as a powerful tool that satiates such Integrated Circuit (IC) package requirements. 3-D looks to be the future of hand-held electronics; hence, making it an important research area. Access to the third dimension has significantly simplified chip-level communications and transfer of information among the processing elements and has provided rapid access to memory and configurable logic. The active devices are confined to a plane in the upper surface of a semiconductor crystal with several layers of fixed interconnects separated by dielectrics above. As planar device miniaturization continues to its ultimate limits, the complexity of circuit interconnections for 2-D devices becomes a limitation for performance and drives up power dissipation [1]. 3-D technology would enable extremely dense solid-state memory to be arrayed within a few microns of the processing elements, which reduces access times. The 3-D arrangement also provides opportunities for new circuit architectures based on the geometrical ability to have greater numbers of interconnections among multi-layer active circuits. A 3-D FPGA would overcome the interconnect limitations, resulting in greater silicon efficiency per function (number of used gates/total number of gates), faster signal/data throughput, and faster switching of the gate-level configuration. True 3-D integrated circuits can operate at higher clock rates and can consume less power over their 2-D implementations, as the 3-D arrangement minimizes the length of circuit interconnects [1]. Stacking for low-device-interconnects (LDI) has been well developed with current stacks exceeding 15 devices enabled by wire-bonded interconnects. High-density-interconnects (HDI), however, necessitates area array packaging with much higher number of interconnects as well as reduced footprints. Three dimensional (3-D) stacking of the processor and memory components in high computing applications reduces the communication delay in a multi-core system owing to reduced system size and shorter interconnects [2]. The shorter interconnection length between the processing and memory components in a multi-core system lowers the overall system access latencies and boosts the system performance. “Comparing with CSP (chip scale package), which has a silicon efficiency of about 80%; 3-D stacked packages are around 300% without increasing the thickness or the footprint of the package” [3]. Integration in the Z direction is achieved by stacking dies or packages and interconnecting them with WB (wire bonding), FC (flip chip) or TSV (through silicon via) [3]. For a conventional single chip package, heat can be dissipated through the top (spreader and eventually through the heat sink), bottom (through the substrate and eventually PCB). But for a 3-D package commonly used in handheld products, heat dissipation is even more difficult, as the luxury of having a heat sink is not there due to space constraints. However, this 3-D integration of the processors and memory exacerbates the reliability and thermal problems due to high thermal resistance of the stacked designs. To overcome these thermal challenges and provide faster inter-chip electrical interconnection, Through Silicon Via (TSV) technology is being implemented in 3-D electronics. TSV technology for die-on-die interface has the potential of further improving the IC performance and package assembly efficiency. TSVs allow 3-D chips to be interconnected directly and prove to be critical components for enabling high-speed communication between circuits on stacked die. TSVs provide both the thermal and electrical interconnection between the stacked dies. 3-D TSV technology offers many advantages such as shorter interconnect length, higher silicon efficiency, ease of reliability testing and heterogeneous integration of different chips leading to a highly miniaturized footprint [1]. Miniature CMOS image sensor used in mobile phones is one of the early applications of the TSV technology and currently TSV application is emerging in DRAMs, flash memories, network devices, logic, etc., [3,4].

Although the 3-D TSV technology is being termed as the “next big thing” in the semiconductor arena and has the potential of revolutionizing the packaging industry, it has some inherent issues that need to be addressed before it could be implemented in the mainstream electronics industry. TSV fabrication process, thermal management of 3-D TSV packages, chip real estate (CRE) compensation to accommodate TSVs and thermo-mechanical TSV/chip package interaction (CPI) are some of the key issues in this technology. Furthermore, there are a number of processes and methodologies that are considered proprietary and may require licensing agreements and additional fees for their use. Industry roadmaps, however, continue to point toward the eventual use of TSV in developing new generations of high performance system-in-package products [4]. Progress in this area has accelerated through the cooperation and joint development programs between a number of government, industry and technical universities. Figure 1 and 2 show the chip stacking trend and 2-D vs 3-D interconnection, respectively [5, 10]. In this chapter, a review of thermal-mechanical-electrical challenges for 3-D packaging is presented.

Fig. 1. 3D Innovation Roadmap [5].

Fig. 2. 2D vs 3D Interconnect Length Variation [9].

1.2. TSV Fabrication

Emerging 3D chips stacking and MEMS/Sensors packaging technologies are using DRIE (Deep Reactive Ion Etching) to etch through-silicon via (TSV) for advanced interconnections. The interconnection step can be done prior to or post CMOS manufacturing, each requiring different etch process performances. Unlike other techniques, DRIE has the capability to etch feature sizes ranging from sub-micron to millimeter width. The main specificity of the DRIE is that etch rate is sensitive to the total exposed area and the aspect ratio. For the TSV applications, where the total exposed area is lower than 10%, high etch rates are achievable. The fabrication process is shown in Figure 3 [4]. There will be significant investment required in the equipment and process for via ablation, mask and coating systems, precision imaging systems, alloy plating and chemical etching systems.

Through Silicon Via ablation process variations include:

• Via-first integration forms TSV holes in the basic silicon wafer prior front end semiconductor processing

• Via-middle integration forms the small via holes in the wafer following front-end transistor formation and local interconnect processes

• Via-last hole information and plating processes are performed from the backside surface following wafer thinning

After the formation of holes they are filled with a conductive polymer or plated closed with copper using an electroplating process. The copper via filling process is achieved through a number of alloy deposition steps that begin with applying a thin adhesion layer to the wafers surface and via features using an RF magnetron sputtering process. This is followed by a metal-organic compound deposition to provide a conformal, continuous, and low resistivity Cu seed layer.Electroplating is finally performed using a copper sulfa mate plating solution. Me...

Table of contents

• Cover
• Half Title
• Title Page
• Copyright
• Foreword to the Encyclopedia of Thermal Packaging
• Dedication
• Contents
• Chapter 1. A Review of Cooling Road Maps for 3D Chip Packages
• Chapter 2. Thermal Performance Mapping of Direct Liquid Cooled 3D Chip Stacks
• Chapter 3. Dynamic Thermal Management Considering Accurate Temperature-Leakage Interdependency
• Chapter 4. Energy Reduction and Performance Maximization Through Improved Cooling
• Chapter 5. Optimal Choice of Heat Sinks from an Industrial Point of View
• Chapter 6. Synthetic Jets for Heat Transfer Augmentation in Microelectronics Systems
• Chapter 7. Recent Advance in Thermoelectric Devices for Electronics Cooling
• Chapter 8. Energy Efficient Solid-State Cooling for Hot Spot Removal
• Chapter 9. An Overview of the Use of Phase Change Materials for the Thermal Management of Transient Portable Electronics: Benefits and Challenges
• Chapter 10. Estimation of Cooling Performance of Phase Change Material (Pcm) Module
• Chapter 11. Optimization Under Uncertainty for Electronics Cooling Design
• Chapter 12. Hydrophilic Cnt-Sintered Copper Composite Wick for Enhanced Cooling
• Chapter 13. A Cabinet Level Thermal Test Vehicle to Evaluate Hybrid Double-Sided Cooling Schemes
• Chapter 14. Energy Efficiency and Reliability Risk Mitigation of Data Centers Through Prognostics and Health Management
• Chapter 15. Damage Pre-Cursors Based Assessment of Accrued Thermo-mechanical Damage and Remaining Useful Life in Field Deployed Electronics
• Chapter 16. Towards Embedded Cooling - Gen 3 Thermal Packaging Technology
• Author Index
• Subject Index
• Cover
• Half Title
• Title Page
• Copyright
• Foreword to the Encyclopedia of Thermal Packaging
• Preface
• Contents
• Acknowledgements
• Chapter 1. Data Centers and Thermal Management Approaches
• Chapter 2. Thermal Modeling of Data Centers
• Chapter 3. Dynamic Thermal Modeling of Data Centers
• Chapter 4. Containment
• Chapter 5. Multi-scale Modeling of Electronics Cabinets
• Chapter 6. Thermal Measurements and Their Use in Data Centers
• Author Index
• Subject Index
• Cover
• Half Title
• Title Page
• Copyright
• Dedication
• Foreword to the Encyclopedia of Thermal Packaging
• Preface
• Contents
• Acknowledgements
• Chapter 1. Fundamentals of Electronic Component Thermal Resistance
• Chapter 2. Historical Overview of Proposals for Enhanced Thermal Metrics
• Chapter 3. Star-Shaped Compact Models Including 2R Models
• Chapter 4. Boundary-Condition-Independent Compact Models
• Chapter 5. Theoretical Framework of Compact Thermal Models — Steady Problems
• Chapter 6. Techniques to Create Compact Thermal Models — Steady State Problems
• Chapter 7. Techniques to Create Compact Thermal Models — Dynamic Problems
• Chapter 8. Experimental Calibration of Compact Thermal Models
• Chapter 9. Compact Thermal Models in Practice
• Chapter 10. Standardization Aspects of IC and LED Compact Models
• Chapter 11. Concluding Remarks
• Appendix. A Nomenclature of Thermal Resistance
• Appendix B. Glossary of Frequently Used Terms and Acronyms
• Appendix C. Testing and Characterization Standards for Chip Packages
• Appendix D. Green’s Function for Conduction Equation
• Appendix E. Eliminating Temperature Dependence of Thermal Conductivity
• Author Index
• Subject Index
• Cover
• Half Title
• Title Page
• Copyright
• Foreword to the Encyclopedia of Thermal Packaging
• Preface
• Contents
• Chapter 1. Thermal Challenges
• Chapter 2. Thermally-Aware Design
• Chapter 3. Runtime Thermal Management Techniques
• Chapter 4. Ongoing Efforts
• Author Index
• Subject Index
• About the Authors
• About the Editor-in-Chief