An introductory text to computer architecture, this comprehensive volume covers the concepts from logic gates to advanced computer architecture. It comes with a full spectrum of exercises and web-downloadable support materials, including assembler and simulator, which can be used in the context of different courses. The authors also make available a hardware description, which can be used in labs and assignments, for hands-on experimentation with an actual, simple processor.
This unique compendium is a useful reference for undergraduates, graduates and professionals majoring in computer engineering, circuits and systems, software engineering, biomedical engineering and aerospace engineering.
--> Sample Chapter(s) Chapter 1: Digital Representation of Information
Request Inspection Copy
--> Contents:
Preface
Digital Representation of Information
Logic Functions
Physical Implementation of Logic Circuits
Combinational Modules of Medium Complexity
Arithmetic Circuits
Basic Sequential Circuits
Analysis and Design of Sequential Circuits
Register Transfers and Datapaths
Computer Architecture
Instruction Set Architectures
Programming in Assembly Language
Internal Structure of a Processor
Memory Systems
Inputs, Outputs and Communications
Advanced Computer Architecture Topics
--> --> Readership: Professionals, researchers, academics, undergraduate and graduate students in computer engineering, circuits & systems, software engineering, biomedical engineering and aerospace engineering. --> Computer Architecture;Digital Systems;Digital Circuits;Digital Logic;Microprocessors;Logig Gates;Sequential Circuits;Combinational Circuits;Binary Arithmetic;Arithmetic and Logic Unit;Pipelines00
Frequently asked questions
Yes, you can cancel anytime from the Subscription tab in your account settings on the Perlego website. Your subscription will stay active until the end of your current billing period. Learn how to cancel your subscription.
No, books cannot be downloaded as external files, such as PDFs, for use outside of Perlego. However, you can download books within the Perlego app for offline reading on mobile or tablet. Learn more here.
Perlego offers two plans: Essential and Complete
Essential is ideal for learners and professionals who enjoy exploring a wide range of subjects. Access the Essential Library with 800,000+ trusted titles and best-sellers across business, personal growth, and the humanities. Includes unlimited reading time and Standard Read Aloud voice.
Complete: Perfect for advanced learners and researchers needing full, unrestricted access. Unlock 1.4M+ books across hundreds of subjects, including academic and specialized titles. The Complete Plan also includes advanced features like Premium Read Aloud and Research Assistant.
Both plans are available with monthly, semester, or annual billing cycles.
We are an online textbook subscription service, where you can get access to an entire online library for less than the price of a single book per month. With over 1 million books across 1000+ topics, we’ve got you covered! Learn more here.
Look out for the read-aloud symbol on your next book to see if you can listen to it. The read-aloud tool reads text aloud for you, highlighting the text as it is being read. You can pause it, speed it up and slow it down. Learn more here.
Yes! You can use the Perlego app on both iOS or Android devices to read anytime, anywhere — even offline. Perfect for commutes or when you’re on the go. Please note we cannot support devices running on iOS 13 and Android 7 or earlier. Learn more about using the app.
Yes, you can access Computer Architecture by Guilherme Arroz, José Monteiro, Arlindo Oliveira in PDF and/or ePUB format, as well as other popular books in Computer Science & Systems Architecture. We have over one million books available in our catalogue for you to explore.
This chapter is focused on the ways computers represent information in digital format. In particular, it discusses the mechanisms used to represent various quantities in a digital computer. The digital electronic circuits that are commonly used in a digital computer can assume only one of two possible values, which implies that different quantities have to be represented in a format compatible with this restriction.
We will start by describing how integers are represented, both in the decimal number system, which is familiar to everybody and in other number systems more adequated to be manipulated by computers. In this chapter, this study is limited to non-negative integers and non-negative fractional numbers.
The chapter begins with Section 1.1, where we study binary, octal and hexadecimal number systems. Section 1.2 focuses on studying the foundations of binary arithmetic. Section 1.3 deals with the use of codes, both numeric (with emphasis on decimal codes) as well as alphanumeric (to represent other types of information). Section 1.4 concludes the chapter with some basic concepts on the organisation of binary representation of information.
1.1Number Systems
This chapter deals with the representation of non-signed integer and fractional numbers. Later, in Chapter 5, this subject will be reconsidered to address the representation of signed integer and real numbers. The representation of numbers in digital systems has to be undertaken considering that they use devices which can represent only two possible values.
Given that the common representation of numbers is based on the utilisation of a decimal number system, using base-10, it is natural to consider that the representation of numbers in digital systems may be made using the binary system, using base-2. The base is the number of digits used to represent a number under a given number system.
The general case of representation using a generic base-b will be studied first, followed by the study of the base-2 case.
1.1.1Representation of Integers in Base-b
The representation of a non-signed integer in base-10 is made using a sequence of digits. The number 435, for example, is represented by the sequence of digits 4, 3 and 5. The interpretation of the representation of a number results, firstly, from the digits used and, secondly, from their position within the sequence. As is evident, 435 ≠ 354, even though the digits used are the same.
The position of the digits indicates the weight for each digit. In the previous example, because the digit 4 is in the third position from the right, this means, in fact, four hundreds. The digit 3 represents three tens, and 5 represents five units. This system of representation of numbers is referred as positional.
This analysis can be stated more formally as follows:
or, expressing the powers of 10 involved,
which is a more general way of representation, emphasising the powers of the base.
The number 435 is said to be represented in base-10 since it results from the sum of consecutive powers of 10, each multiplied by the value of the corresponding digit as shown in Equation (1.2). To explicitly indicate that the number is represented in base-10, the following notation is used: 43510. To represent a number in base-10, the weights of each power of 10 are indicated using digits from 0 to 9, using a total of 10 distinct digits.
There is nothing to prevent the use of another base to represent a number. Consider, for example, the sequence of digits 1161 in base-7, which is usually indicated by 11617. In this case, this representation has the following meaning:
Therefore, 11617 is another way of representing the number 43510.
Generally speaking, any integer N can be represented in any base-b with b ≥ 2
or
where pj is the digit which represents the weight of the jth power of the base. The number of digits necessary is b and it is usual that the digits are the integers between 0 and b − 1
Thus, to represent numbers in base-b, digits of a value equal to or greater than b cannot be used. For example, the representation of a number in base-7 cannot use the digit 7 nor any other digit greater than 7. The sequence of digits 17427 is therefore not a valid representation of a number.
The conversion of the representation of a number in base-b to a representation in base-10 is not difficult, as illustrated by Equation (1.3). The reverse, converting a number represented in base-10 to its representation in base-b requires a little more work, but it is also simple. One of the most common methods is the method of successive divisions. As an example, consider a number N represented in base-b, as shown in Equation (1.4). If the number is divided by b, this results in
where p0 is the rest of the division of N by b (remember that p0 < b). In this way, the digit p0 can be identified.
Repeating the previous procedure for the number
will enable us to derive p1 and through the successive application of the procedure, all the digits that represent the number.
As an example, consider obtaining the representation of the number 27310 in base-5
In the same way, the following can be ...
Table of contents
Cover Page
Title Page
Copyright Page
Preface
Contents
1. Digital Representation of Information
1.1 Number Systems
1.1.1 Representation of Integers in Base-b
1.1.2 Representation of Non-signed Integers in Base-2
1.1.3 Representation of Fractional Numbers in Base-2
1.1.4 Representation of Numbers in Bases Powers of 2
1.2 Arithmetic Operations in Base-2, Base-8 and Base-16
1.2.1 Sums in Base-2
1.2.2 Multiplications in Base-2
1.2.3 Arithmetic Operations in Other Bases
1.3 Codes
1.3.1 Coding
1.3.2 Numeric Codes
1.3.3 Reflected Codes
1.3.4 Alphanumeric Codes
1.4 Units of Information
1.5 Summary
Exercises
2. Logic Functions
2.1 Binary Boolean Algebra
2.1.1 One-variable Logic Functions
2.1.2 Two-variable Logic Functions
2.1.3 The Functions AND and OR
2.1.4 Conjunction or AND Function
2.1.5 Disjunction or OR Function
2.1.6 Duality Principle
2.1.7 Operation Priority
2.1.8 Theorems Involving AND and OR
2.1.9 Formal Definition of Boolean Algebra
2.1.10 NAND and NOR Functions
2.1.11 XOR Function
2.1.12 N-variable Logic Functions
2.1.13 Handling of Logic Expressions
2.2 Representation of Logic Functions
2.2.1 Standard Sum of Products Form
2.2.2 Standard Product of Sums Form
2.2.3 Representation of Functions Using a Single Operator Type
2.3 Minimising Logic Expressions
2.3.1 Karnaugh Method
2.3.1.1 Motivation for the Karnaugh method
2.3.1.2 Three-variable Karnaugh map
2.3.1.3 Four-variable Karnaugh map
2.3.2 Foundations of the Karnaugh Method
2.3.3 Karnaugh Method for Incompletely Specified Functions
2.3.4 Five-variable Karnaugh map
2.3.5 Quine–McCluskey Method
2.3.6 Quine–McCluskey Method for Incompletely Specified Functions
2.3.7 Comparison between Karnaugh and Quine–McCluskey Methods
2.4 Summary
Exercises
3. Physical Implementation of Logic Circuits
3.1 Digital Integrated Circuits
3.1.1 Logic Families
3.1.2 Basic Gates
3.1.3 Logic Levels and Voltage Levels
3.1.4 Delays
3.1.5 Power
3.1.6 Special Devices
3.1.6.1 Tri-state buffers
3.1.6.2 Incomplete devices
3.1.6.3 Transmission gates
3.2 Positive, Negative and Polarity Logic
3.3 Circuit Wiring Diagrams
3.4 Timing Characteristics
3.4.1 Analysis of Delays in Circuits
3.4.2 Spurious Transitions in Combinational Circuits
3.5 Direct Implementation
3.5.1 Implementation Using ROMs
3.5.2 Implementation Using Programmable Logic Arrays
3.5.3 Implementation Using Programmable Array Logic
3.6 Summary
Exercises
4. Combinational Modules of Medium Complexity
4.1 Modularity
4.2 Decoders
4.2.1 Binary Decoders
4.2.2 Decoder Expansion
4.3 Encoders
4.3.1 Binary Encoders
4.4 Multiplexers
4.4.1 Implementation of Multiplexers
4.4.2 Types of Multiplexers
4.4.3 Expansion of Multiplexers
4.4.4 Multiplexing and Demultiplexing
4.5 Implementation of Logic Functions with Modules of Medium Complexity
4.5.1 Implementation with Decoders
4.5.2 Implementation with Multiplexers
4.6 Iterative Circuits
4.7 Summary
Exercises
5. Arithmetic Circuits
5.1 Adders
5.1.1 Half-Adder
5.1.2 Full-Adder
5.1.3 N-bit Adder
5.1.4 Fast Adders
5.1.4.1 Carry-select adders
5.1.4.2 Carry-lookahead adders
5.2 Signed Numbers
5.2.1 Sign and Magnitude Encoding
5.2.2 2’s Complement Encoding
5.2.3 Sign Extension
5.2.4 Operations with Numbers in 2’s Complement
5.2.5 Overflow
5.2.6 Subtractors
5.2.7 Subtractor Circuit
5.2.8 Subtraction Using Adders
5.2.9 Adder/Subtractor Circuit
5.3 Multipliers and Dividers
5.3.1 Multiplication of Unsigned Numbers: Array Multiplier
5.3.2 Analysis of the Array Multiplier Circuit
5.3.3 Multiplication of Signed Numbers
5.3.4 Multiplication of Numbers in Sign-Magnitude Representation
5.3.5 Multiplication of Numbers in 2’s Complement Notation
5.3.6 Divisors
5.4 Fixed-Point
5.4.1 Fixed-Point Representation
5.4.2 Operations Under Fixed-Point Using Integer Units
5.4.3 Limitations of Fixed-Point Representation
5.5 Floating-Point Representations
5.5.1 Mantissa and Exponent
5.5.2 Floating-Point Operations
5.5.3 IEEE-754 Standard
5.6 Summary
Exercises
6. Basic Sequential Circuits
6.1 Sequential Behaviour of Circuits
6.2 Latches
6.2.1 SR Latch
6.2.2 SR Latches with an Enable Signal
6.2.3 D Latch
6.3 Clock Signal
6.3.1 Global Synchronisation Signal
6.3.2 Characteristics of the Clock Signal
6.4 Flip-Flops
6.4.1 Types of Sampling
6.4.1.1 Masterr–slave flip-flops
6.4.1.2 Edge-triggered flip-flops
6.4.2 Types of Flip-Flops
6.4.2.1 D-type flip-flops
6.4.2.2 SR flip-flops
6.4.2.3 JK flip-flops
6.4.2.4 T flip-flops
6.4.3 Direct Inputs
6.4.4 Timing Parameters of Flip-Flops
6.5 Registers
6.5.1 Basic Registers
6.5.2 Register Control Signals
6.5.3 Shift Registers
6.5.4 Status Signals in Registers
6.6 Counters
6.6.1 Asynchronous Counters
6.6.1.1 Timing diagram
6.6.1.2 Maximum operating frequency
6.6.1.3 Asynchronous counter with a generic modulo
6.6.2 Synchronous Counters
6.6.2.1 Transient states in synchronous counters
6.6.2.2 Maximum operating frequency
6.6.2.3 Count control signal
6.6.2.4 Counters as registers
6.6.2.5 Synchronous counters with an arbitrary modulo
6.6.2.6 Synchronous counters with an arbitrary sequence
6.6.3 Interconnection of Counters
6.6.4 Applications of Counters
6.7 Register Transfers
6.7.1 Interconnection Using Multiplexers
6.7.2 Interconnection Using a Single Bus
6.7.3 Register Files
6.8 Memories
6.8.1 Random Access Memories
6.8.1.1 Random access memory operation
6.8.1.2 Comparison with a register file
6.8.1.3 Internal structure
6.8.2 Dynamic Memories
6.8.3 FIFO Memories
6.9 Summary
Exercises
7. Analysis and Design of Sequential Circuits
7.1 Synchronous and Asynchronous Sequential Circuits
7.2 Mealy and Moore Machines
7.3 Design of Synchronous Sequential Circuits
7.3.1 State Diagrams
7.3.1.1 State diagram for the parity detector
7.3.1.2 State diagram for an alarm detector
7.3.2 Elimination of Redundant States
7.3.3 Specification Using Flowcharts
7.4 Implementation of Synchronous Sequential Circuits
7.4.1 State Assignment
7.4.1.1 State assignment using binary code
7.4.1.2 Encoding with one flip-flop per state
7.4.2 State Transition Table
7.4.3 Circuit Synthesis
7.4.3.1 Synthesis using D-type flip-flops
7.4.3.2 Circuit synthesis using JK flip-flops
7.4.3.3 Synthesis using one flip-flop per state
7.5 Techniques for the Implementation of Complex Sequential Circuits
7.5.1 Control Unit Implemented with Discrete Logic
7.5.2 Counter-based Control Units
7.5.3 Microprogrammed Control Unit
7.6 Summary
Exercises
8. Register Transfers and Datapaths
8.1 Levels of Abstraction
8.2 Separation between Datapath and Control Circuit
8.2.1 Motivation Example
8.2.2 Datapath
8.2.3 Control Unit
8.3 Hardware Description Language
8.3.1 Register Transfer Language
8.3.2 Example: Greatest Common Divisor
8.4 Arithmetic Logic Units
8.4.1 Structure of an ALU
8.4.2 Flags
8.4.3 Arithmetic Unit
8.4.4 Logic Unit
8.4.5 Shift Unit
8.4.6 ALU Control Table
8.4.7 Example Revisited: Greatest Common Divisor
8.5 Summary
Exercises
9. Computer Architecture
9.1 Historical Perspective
9.2 Types of Computers
9.3 Types of Processors
9.4 Internal Organisation of a Computer
9.5 Internal Structure of a Processor
9.6 External Interaction
9.7 Computer Abstraction Levels
9.8 Computer Components
9.9 Summary
Exercises
10. Instruction Set Architectures
10.1 Programming Languages
10.2 Assembly Instructions
10.3 Specification of Operands
10.3.1 Internal Registers
10.3.2 Constants Specified in the Instruction
10.3.3 Memory and Input/Output Ports
10.3.4 Addressing Modes
10.3.5 Use of Stacks
10.3.6 Types of Operands
10.4 Instruction Encoding
10.5 Program Control Instructions
10.5.1 Jump Instructions
10.5.1.1 Conditional jumps
10.5.1.2 Absolute jumps and relative jumps
10.5.2 Subroutine Calls
10.5.3 Interrupts
10.6 Instruction Set for the P3 Processor
10.6.1 Arithmetic Instructions
10.6.2 Logic Instructions
10.6.3 Shift Instructions
10.6.4 Control Instructions
10.6.5 Data Transfer Instructions
10.6.6 Other Instructions
10.6.7 Examples of Use
10.7 Instruction Format for the P3 Processor
10.7.1 Instructions with No Operands
10.7.2 Instructions with One Operand
10.7.3 Instructions with Two Operands
10.7.4 Control Instructions
10.7.5 Encoding Examples
10.8 An Assembler for the P3 Processor
10.9 Summary
Exercises
11. Programming in Assembly Language
11.1 Translation of High-level Language Constructs to Assembly
11.1.1 Variables
11.1.1.1 Simple types
11.1.1.2 Compound types
11.1.1.3 Arrays
11.1.1.4 Pointers
11.1.1.5 Variables in registers
11.1.2 Data Manipulation
11.1.2.1 Same width for variables and data word
11.1.2.2 Width of variables narrower than the data word
11.1.2.3 Width of variables wider than the data word
11.1.2.4 Floating-point data types
11.1.3 Control Structures
11.1.4 Subroutine Calls
11.1.4.1 Parameter passing using registers
11.1.4.2 Parameter passing using the memory
11.1.4.3 Parameter passing using the stack
11.2 Programming Techniques in Assembly
11.2.1 Structured Programming
11.2.2 Comments
11.2.3 Constants
11.2.4 Formatting Code
11.3 Programming Examples
11.3.1 List Manipulation
11.3.2 State Machine
11.4 Complete Illustrative Example
11.5 Summary
Exercises
12. Internal Structure of a Processor
12.1 Datapath
12.1.1 Register File
12.1.2 Arithmetic Logic Unit
12.1.3 Instruction Register
12.1.4 Status Register
12.1.5 Interconnection Buses
12.1.6 Datapath Control
12.2 Control Unit
12.2.1 Microinstruction Format
12.2.2 Microsequencer
12.2.3 Conditions Test
12.2.4 Mapping Unit
12.2.5 Register File Control
12.2.6 Control Circuit
12.3 Microprogramming
12.3.1 Instruction Fetch
12.3.2 Operand Fetch
12.3.3 Execution of Instructions
12.3.4 Write Back
12.3.5 Testing for Interrupts
12.3.6 Generating the Microcode
12.4 Summary
Exercises
13. Memory Systems
13.1 Organisation of Memory Systems
13.1.1 Memory Banks
13.1.2 Memory Maps
13.1.3 Generation of Control Signals
13.2 Memory Hierarchy
13.2.1 Caches
13.2.2 Virtual Memory
13.3 Organisation of Cache Systems
13.3.1 Cache Data Mapping
13.3.2 Cache Blocks
13.3.3 Replacement Policies
13.3.4 Write Policies
13.3.5 Control Bits
13.4 Virtual Memory
13.4.1 Page Tables
13.4.1.1 Flat page table
13.4.1.2 Hierarchical page table
13.4.2 Replacement Policy
13.4.3 Write Policy
13.4.4 Control Bits
13.4.5 Translation Lookaside Buffers
13.4.6 Interconnection of Virtual Memory with the Caches
13.5 Summary
Exercises
14. Inputs, Outputs and Communications
14.1 Input/Output Architecture
14.1.1 Interfaces
14.1.2 Port Addressing Types
14.2 Peripherals
14.2.1 Keyboards
14.2.2 Monitors
14.2.3 Magnetic Disks and Solid-state Drives
14.3 Parallel Communication
14.3.1 Interfaces without Synchronisation
14.3.2 Data Strobing and Handshaking
14.3.2.1 Strobe synchronisation
14.3.2.2 Handshake protocols
14.3.3 Synchronous Interfaces
14.4 Serial Communications
14.4.1 Asynchronous Communication
14.4.2 Synchronous Communication
14.4.2.1 Character oriented protocols
14.4.2.2 Bit-oriented protocols
14.5 Interruption System
14.5.1 Interrupts Operation
14.5.2 Independent Interrupt Lines
14.5.3 Shared Interrupt Line
14.5.3.1 Non-vectored interrupts
14.5.3.2 Vectored interrupts
14.6 Data Transfer Modes
14.6.1 Program Controlled Transfer
14.6.2 Interrupt Controlled Transfer
14.6.3 Direct Memory Access
14.6.3.1 DMA architecture
14.6.3.2 The DMA controller
14.6.3.3 Types of DMA
14.6.4 Transfer Using an Input/Output Processor
14.7 Summary
Exercises
15. Advanced Computer Architecture Topics
15.1 Microprocessor Performance
15.1.1 Limiting Performance Factors
15.1.2 CISC and RISC Computers
15.2 The P4 Processor
15.2.1 Addressing Modes
15.2.2 P4 Processor Instruction Set
15.2.2.1 Arithmetic and logic instructions
15.2.2.2 Shift instructions
15.2.2.3 Control instructions
15.2.2.4 Data transfer instructions
15.2.2.5 Other instructions
15.3 The P4 Processor Pipeline
15.3.1 Stages in the P4 Processor Pipeline
15.3.1.1 Instruction fetch
15.3.1.2 Decoding of the operation code and operand fetch
15.3.1.3 Instruction execution
15.3.1.4 Write-back
15.3.2 P4 Processor Complete Pipeline
15.3.3 Structural Conflicts
15.3.4 Data Conflicts
15.3.5 Control Conflicts
15.4 Performance Comparison between P3 and P4
15.5 Advanced Techniques for Exploiting Parallelism
