High Performance Logic and Circuits for High-Speed Electronic Systems

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F Jain, C Broadbridge;M Gherasimova;H Tang

• Publisher: WSPC
• Year: 2019
• eBook ISBN: 9789811208454
• Topic: Technology & Engineering
• Subtopic: Electrical Engineering & Telecommunications
• Index: Technology & Engineering

In this volume, we have put together papers spanning a broad range — from the area of modeling of strain and misfit dislocation densities, microwave absorption characteristics of nanocomposites, to X-ray diffraction studies.

Specific topics in this volume include:

In summary, papers selected in this volume cover various aspects of high performance logic and circuits for high-speed electronic systems.

Contents:

• Preface
• Modeling and Control of a Multiphase Modular High-Frequency Converter/Inverter for Vehicle Applications (K Ahi)
• Macromodel of G⁴FET Enabling Fast and Reliable SPICE Simulation for Innovative Circuit Applications (M S Hasan, S Shamsir, S A Shawkat, F Garcia, S K Islam and G S Rose)
• Multivariate Regression Polynomial: A Versatile and Efficient Method for DC Modeling of Different Transistors (MOSFET, MESFET, HBT, HEMT and G⁴FET) (M S Hasan, S Shamsir, S A Shawkat, F Garcia and S K Islam)
• A SPICE Model for GaN-Gate Injection Transistor (GIT) at Room Temperature (F Garcia, S Shamsir, S K Islam and L M Tolbert)
• Perimeter Gated Single Photon Avalanche Diodes in Sub-Micron and Deep-Submicron CMOS Processes (S A Shawkat, M H U Habib, M S Hasan, M A Haque and N McFarlane)
• A Novel One SWS-FET Transistor for AND/OR Logic Gate (B Saman, E Heller and F C Jain)
• Multi-State 2-Bit CMOS Logic Using n- and p- Quantum Well Channel Spatial Wavefunction Switched (SWS) FETs (F Jain, B Saman, R H Gudlavalleti, J Chandy and E Heller)
• Low Pass Filter PUF: Authentication of Printed Circuit Boards Based on Resistor and Capacitor Variations (S E Quadir and J A Chandy)
• Interaction Length for Dislocations in Compositionally-Graded Heterostructures (M Cai, T Kujofsa, X Chen, M T Islam and J E Ayers)
• Optimization of Graded Buffer Layers for Metamorphic Semiconductor Devices (T Kujofsa, M Cai, X Chen, M T Islam and J E Ayers)
• Twin Drain Quantum Well/Quantum Dot Channel Spatial Wave-Function Switched (SWS) FETs for Multi-Valued Logic and Compact DRAMs (H Salama, B Saman, E Heller, R H Gudlavalleti, R Mays and F Jain)
• A Rapid Method Based on Fluorescence Spectroscopy for Meat Spoilage Detection (B Wu, K Dahlberg, X Gao, J Smith and J Bailin)
• Optical Biopsy for Prostate Cancer Diagnosis Using Fluorescence Spectroscopy (B Wu, X Gao and J Smith)
• Fast and Reversible Chemiresistive Sensors for Robust Detection of Organic Vapors Using Oleylamine-Functionalized Palladium Nanoparticles (T Gao, Y Wang, Y Luo, C Zhang, Z Pittman, A Oliveira, H Craig, J Zhao and B G Willis)
• Threading Dislocations in Metamorphic Semiconductor Buffer Layers Containing Chirped Superlattices (M T Islam, X Chen, T Kujofsa and J E Ayers)

Readership: This volume consists of selected papers from the 27th annual symposium of the Connecticut Microelectronics and Optoelectronics Consortium. Readers interested in the area of modeling of strain and misfit dislocation densities, microwave absorption characteristics of Nanocomposites, and X-ray diffraction.Misfit Dislocation Densities;Nanocomposites;CMOS-SWS Logic;Perimeter Gated Single-Photon Avalanche Diode (PGSPAD)00

Macromodel of G⁴FET Enabling Fast and Reliable SPICE Simulation for Innovative Circuit Applications

Md Sakib Hasan*, Samira Shamsir, Mst Shamim Ara Shawkat, Frances Garcia, Syed K. Islam and Garrett S. Rose

Department of Electrical Engineering and Computer Science, The University of Tennessee, Knoxville, TN 37996, USA

*[email protected]

A macromodel of silicon-on-insulator (SOI) four-gate transistor (G⁴FET) is presented in this paper to aid circuit designers to explore innovative applications circuit with this multi-gate transistor. A number of works based on analytical solution, numerical simulation and experimental results of G⁴FET have been previously reported. However, designing new interesting circuits with G⁴FETs requires a SPICE model that will work sufficiently well throughout the desired operating regions. Although it is theoretically possible to solve coupled non-linear differential equations to explore different operating conditions, this will take an excessive amount of time making it unsuitable for useful circuit design. Therefore, a macromodel approach is adopted in this work to provide a reasonably fast and accurate circuit simulation. G⁴FET combines the functionality of MOSFET and JFET devices which already have robust, fast and reliable SPICE models. A macromodel approach which is capable of combining these existing models including the interactions between multiple gates will be beneficial for any circuit designer. The feasibility of the macromodel is justified by simulating several analog and digital circuits and comparing against available experimental results.

Keywords: Silicon-on-insulator (SOI); multiple-gate transistor; G⁴FET; semiconductor device models; SPICE; macromodel.

1. Introduction

There have been amazing technological advancements in semiconductor industries over the last several decades following Moore’s law [1]. However, scaling down bulk silicon devices has become increasingly difficult and is now facing some fundamental physical limits. Some of the non-idealities such as subthreshold conduction, gate oxide leakage, threshold voltage roll-off due to DIBL (drain induced barrier lowering), reduced carrier mobility due to impurity scattering by increased doping concentration, slowing down of switching time scaling due to more dominant role played by interconnect capacitance, reverse-biased junction leakage etc. can no longer be ignored. To solve the problems associated with bulk silicon scaling and enable the semiconductor industry to extend Moore’s law in the foreseeable future, researchers have been searching for new process technologies. One of the promising candidates is silicon-on-insulator (SOI) technology with many advantages such as ideal device isolation, reduced parasitic capacitance, excellent sub-threshold slope, elimination of latch up, increased switching speed, radiation hardness, reduced leakage current etc. [2]. A recent SOI device with multiple gates that has been used for several innovative circuit designs is G⁴FET [3, 4]. The name G⁴FET came from its four independent gates, two of which provide vertical MOS (metal-oxide-semiconductor) field-effect action whereas the other two gates provide lateral junction field effect transistor (JFET) functionality. The unique G⁴FET structure can be leveraged to design circuits for different analog, mixed-signal and digital applications with significantly reduced transistor counts. Some of these have already been experimentally demonstrated including LC oscillators and Schmitt trigger circuit with adjustable hysteresis using negative differential resistance [5], high voltage current mirrors and differential amplifiers [6], four quadrant analog multipliers [7], adjustable threshold inverters, real time reconfigurable logic gates and DRAM cell [8], universal and programmable logic gate capable of highly efficient full adder design [9], and temperature compensated voltage references [10]. Another exciting application is the formation of quantum wire with low subthreshold swing, high mobility and low noise in depletion-all-around action when the vertical MOS gates and lateral JFET gates are used simultaneously to create a conducting channel surrounded by depletion regions [11]. G⁴FET inspired multiple state electro-statically formed nanowires have already been used for threshold logic functions [12, 13], femtomolar bio-marker detection [14] and high-sensitivity gas sensing [15].

A G⁴FET transistor can operate in different regimes based on the bias voltages on its four gates and the silicon epi layer thickness. A SPICE model that can work sufficiently well throughout the different operating regions and different types of simulations is absolutely necessary to design innovative circuits with G⁴FETs. Although a number of works on G⁴FET modeling have been reported in the literature, so far, it has not been possible to come up with a reasonably concise compact model based on device physics which is valid for different combinations of gate biases. It is theoretically possible to solve coupled non-linear differential equations describing device operation to explore different operating conditions. But this will take prohibitively long time and therefore, is not suitable for useful circuit design. However, we can find in the literature that G⁴FET has previously been called MOSJFET [4] since it combines both metal-oxide-semiconductor field-effect transistor (MOSFET) and junction field-effect transistor (JFET) actions in a single body. This is motivation behind this proposed approach to combine existing MOSFET and JFET models for building a macromodel where the interactions between different gates are accounted for using analytical expression from device physics. This approach can provide reasonably fast and accurate DC, transient and AC circuit simulation.

The remainder of the paper is as follows — a brief summary of prior works on macromodels and G⁴FET modeling is given in Sec. 2. Section 3 describes the device structure and operating principle of G⁴FET. The model formulation is described in Sec. 4. Section 5 describes the resul...

Table of contents

• Cover page
• Title page
• Copyright
• Preface
• Contents
• Modeling and Control of a Multiphase Modular High-Frequency Converter/Inverter for Vehicle Applications
• Macromodel of G4FET Enabling Fast and Reliable SPICE Simulation for Innovative Circuit Applications
• Multivariate Regression Polynomial: A Versatile and Efficient Method for DC Modeling of Different Transistors (MOSFET, MESFET, HBT, HEMT and G4FET)
• A SPICE Model for GaN-Gate Injection Transistor (GIT) at Room Temperature
• Perimeter Gated Single Photon Avalanche Diodes in Sub-Micron and Deep-Submicron CMOS Processes
• A Novel One SWS-FET Transistor for AND/OR Logic Gate
• Multi-State 2-Bit CMOS Logic Using n- and p-Quantum Well Channel Spatial Wavefunction Switched (SWS) FETs
• Low Pass Filter PUF: Authentication of Printed Circuit Boards Based on Resistor and Capacitor Variations
• Interaction Length for Dislocations in Compositionally-Graded Heterostructures
• Optimization of Graded Buffer Layers for Metamorphic Semiconductor Devices
• Twin Drain Quantum Well/Quantum Dot Channel Spatial Wave-Function Switched (SWS) FETs for Multi-Valued Logic and Compact DRAMs
• A Rapid Method Based on Fluorescence Spectroscopy for Meat Spoilage Detection
• Optical Biopsy for Prostate Cancer Diagnosis Using Fluorescence Spectroscopy
• Fast and Reversible Chemiresistive Sensors for Robust Detection of Organic Vapors Using Oleylamine-Functionalized Palladium Nanoparticles
• Threading Dislocations in Metamorphic Semiconductor Buffer Layers Containing Chirped Superlattices