Understanding Delta-Sigma Data Converters

Shanthi Pavan, Richard Schreier, Gabor C. Temes

• Publisher: Wiley-IEEE Press
• Year: 2016
• Print ISBN: 9781119258278
• eBook ISBN: 9781119258292
• Edition: 2
• Topic: Technology & Engineering
• Subtopic: Electrical Engineering & Telecommunications
• Index: Technology & Engineering

This new edition introduces operation and design techniques for Sigma-Delta converters in physical and conceptual terms, and includes chapters which explore developments in the field over the last decade

• Includes information on MASH architectures, digital-to-analog converter (DAC) mismatch and mismatch shaping
• Investigates new topics including continuous-time ?? analog-to-digital converters (ADCs) principles and designs, circuit design for both continuous-time and discrete-time ?? ADCs, decimation and interpolation filters, and incremental ADCs
• Provides emphasis on practical design issues for industry professionals

CHAPTER 1

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THE MAGIC OF DELTA-SIGMA MODULATION

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The aim of this introductory chapter is to motivate the need for oversampling data converters, and to give a bird’s-eye view of the topics covered in this book. Towards the end of the chapter, we give a brief overview of the origins of ΔΣ data conversion and trends in this exciting area.

1.1 The Need for Oversampling Converters

Computational and signal processing tasks are now performed predominantly by digital means, since digital circuits are robust and can be realized by extremely small and simple structures that can in turn be combined to obtain very complex, accurate, and fast systems. Every year, the speed and density (of transistors) of digital integrated circuits (ICs) increase, thereby enhancing the dominance of digital methods in almost all areas of communications and consumer products. Since the physical world nevertheless remains stubbornly analog, data converters are needed to interface with the digital signal processing (DSP) core. As the speed and capability of DSP cores increases, so too must the speed and accuracy of the converters associated with them. This presents a continual challenge to the lucky few engineers dedicated to the design of data converters!

Figure 1.1 illustrates the block diagram of a signal processing system with analog input and output signals, plus a central digital engine. As shown, the analog input signal (usually after some amplification and filtering) enters an analog-to-digital converter (ADC), that transforms the input signal into a digital data stream. This stream is processed by the DSP core, and the resulting digital output signal is reconverted into analog form by a digital-to-analog converter (DAC). The DAC output is usually also filtered and amplified to obtain the final analog output signal.

Figure 1.1 ADCs and DACs interface the real world to the virtual world.

Data converters (both ADCs and DACs) can be classified into two main categories: Nyquist-rate and oversampled converters. In the former category, there exists a one-to-one correspondence between the input and output samples. Each input sample is separately processed, regardless of the earlier input samples; in other words, the converter has no memory. Applying a digital input word containing bits b₁, b₂, …, b_N to a Nyquist-rate DAC ideally results in an analog output

(1.1)

where V_ref is the reference voltage, regardless of any previous input word. The accuracy of conversion can be evaluated by comparing the actual value of V_out with the ideal value given by (1.1).

As the name implies, the sampling rate f_s of a Nyquist-rate converter can be as low as Nyquist’s criterion requires, i.e., twice the bandwidth B of the input signal. (For practical reasons, the actual rate is usually somewhat higher than this minimum value.)

In most cases, the linearity and precision of a Nyquist-rate converter is determined by the matching accuracy of the analog components (resistors, current sources, or capacitors) used in the implementation. For example, in the N-bit resistor-string DAC shown in Figure 1.2, the resistors must have a relative matching error less than 2^−N to guarantee an integral nonlinearity (INL)¹ less than 0.5 LSB. Similar matching requirements prevail for ADCs and DACs constructed from current sources or switched-capacitor (SC) branches. Practical conditions restrict the matching accuracy to about 0.02%, and hence the effective number of bits (ENOB) to about 12, for such converters.

Figure 1.2 A resistor-string DAC. LSB denotes the least significant bit and MSB the most significant bit of the digital input.

In many applications (e.g., digital audio), higher resolution and linearity are required, even as much as 18 or 20 bits. The only Nyquist-rate converters capable of such accuracy are the integrating or counting ones. These, however, require at least 2^N clock periods to convert a single sample, and hence, they are too slow for most signal processing applications.

Oversampling data converters are able to achieve over 20 ENOB resolution at reasonably high conversion speeds by relying on a trade-off. They use sampling rates much higher than the Nyquist rate, typically higher by a factor between 8 and 512, and ge...

Table of contents

• Cover
• Series Title Page
• Title Page
• Copyright
• Contents
• Preface
• 1 The Magic of Delta-Sigma Modulation
• 2 Sampling, Oversampling, and Noise-Shaping
• 3 Second-Order Delta-Sigma Modulation
• 4 High-Order Delta-Sigma Modulators
• 5 Multi-Stage and Multi-Quantizer Delta-Sigma Modulators
• 6 Mismatch-Shaping
• 7 Circuit Design for Discrete-Time Delta-Sigma ADCs
• 8 Continuous-Time Delta-Sigma Modulation
• 9 Nonidealities in Continuous-Time Delta-Sigma Modulators
• 10 Circuit Design for Continuous-Time Delta-Sigma Modulators
• 11 Bandpass and Quadrature Delta-Sigma Modulation
• 12 Incremental Analog-to-Digital Converters
• 13 Delta-Sigma DACs
• 14 Interpolation and Decimation Filters
• A Spectral Estimation
• B The Delta-Sigma Toolbox
• C Linear Periodically Time-Varying Systems
• Index
• IEEE PRESS SERIES ON MICROELECTRONIC SYSTEMS
• EULA