Advances in Embedded and Fan-Out Wafer Level Packaging Technologies

Beth Keser, Steffen Kröhnert, Beth Keser, Steffen Kroehnert, Beth Keser, Steffen Kroehnert

• Publisher: Wiley-IEEE Press
• Year: 2019
• Print ISBN: 9781119314134
• eBook ISBN: 9781119313984
• Edition: 1
• Topic: Tecnologia e ingegneria
• Subtopic: Ingegneria elettronica e telecomunicazioni

Examines the advantages of Embedded and FO-WLP technologies, potential application spaces, package structures available in the industry, process flows, and material challenges

Embedded and fan-out wafer level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for nearly a decade. This book covers the advances that have been made in this new packaging technology and discusses the many benefits it provides to the electronic packaging industry and supply chain. It provides a compact overview of the major types of technologies offered in this field, on what is available, how it is processed, what is driving its development, and the pros and cons.

Filled with contributions from some of the field's leading experts, Advances in Embedded and Fan-Out Wafer Level Packaging Technologies begins with a look at the history of the technology. It then goes on to examine the biggest technology and marketing trends. Other sections are dedicated to chip-first FO-WLP, chip-last FO-WLP, embedded die packaging, materials challenges, equipment challenges, and resulting technology fusions.

• Discusses specific company standards and their development results
• Content relates to practice as well as to contemporary and future challenges in electronics system integration and packaging

Advances in Embedded and Fan-Out Wafer Level Packaging Technologies will appeal to microelectronic packaging engineers, managers, and decision makers working in OEMs, IDMs, IFMs, OSATs, silicon foundries, materials suppliers, equipment suppliers, and CAD tool suppliers. It is also an excellent book for professors and graduate students working in microelectronic packaging research.

1
History of Embedded and Fan‐Out Packaging Technology

Michael Töpper, Andreas Ostmann, Tanja Braun, and Klaus‐Dieter Lang

Fraunhofer IZM, Berlin, Germany

1.1 Introduction

The fabrication of microelectronic systems purely monolithically on a wafer is limited by the need for mixed technologies and redundancy. Multi‐chip modules (MCMs) provided an alternative in achieving high density interconnects (HDI) being originally developed in the 1980s for aerospace applications, where size and weight were critical requirements [1]. The core idea of MCM was therefore the reduction of the interconnection length between different electronic components like integrated circuits (ICs), passives, and others like optoelectronic components. In 1990, silicon devices of 16 mm × 16 mm were the limits of manufacturability in volume production – far from the wafer‐scale integration goals necessary for large electronic systems. Therefore, multiple ICs were needed, which resulted in a hybrid manufacturing process. Standard packaging technologies have used single packaged ICs that are mounted on the printed circuit board (PCB). The electrical signals have to travel from the IC through the package and through the PCB to the next package, limiting the high‐speed performance of the systems. This translates to long interconnection lengths between devices and a corresponding increase in propagation delay. MCM was the first approach to eliminate the package and to use a high density routing substrate instead of PCB. All ICs and also the substrates can be pretested to ensure a high yield module process.

The interconnection of the bare ICs to the MCM substrate can be done by direct chip connection using wire bonding (WB), tape‐automated bonding (TAB), or flip‐chip (FC) bonding. The basic MCM concept was first proposed by IBM in 1972 as an “active silicon chip carrier” [2]. There were three main approaches for MCM processes developed: MCM‐laminate (MCM‐L), in which a multilayer prepreg laminated board was used; high density ceramic MCM (MCM‐C), in which a multilayer co‐fired ceramic substrate was used; and thin film deposited MCM (MCM‐D), in which a thin film metal/dielectric substrate was used. The reason for building MCM‐D in the late 1980s will still sound familiar today: providing off‐the‐chip interconnect bandwidth matching the semiconductors clocking rates, decreasing power dissipation in input and output (I/O) drivers with matched impedance, and reducing the volume and size of the circuits. The difference between then and now is a major push for low fabrication costs to satisfy the consumer markets. System in packages (SiP) can therefore be viewed as an extension of an MCM. In addition, the lack of availability of known good die (KGD) for the different applications was a major hurdle to get functional MCMs with a sufficient yield. All of these types were in principle “chip‐last” technologies in which the interconnection substrate is manufactured before the chip attachment being done by FC, WB, or less used TAB. “Chip‐first” is the usage of an embedding process where the chips are placed under the interconnection layer. The chips have to be placed onto or within a base substrate prior to the fabrication of the interconnect structure that is then a direct metallurgical contact eliminating FC, WB, or TAB. With such an electrical interconnect, a reference ground plane can be deposited directly onto the chip pads, which provide a very well‐matched high frequency interconnect structure. The inductance and the capacitance are over 10 times lower compared with FC, TAB, and WB.

Therefore embedding‐type MCMs have been developed to bypass the yield issue for monolithic wafer‐scale integration. Main pioneering work was done by Wayne Johnson from Auburn University and Ray Fillion from GE Research. Johnson et al. proposed a hybrid that uses pretested ICs mounted into cavities etched in a silicon wafer [3]. A schematic of this concept is shown in Figure 1.1.

Figure 1.1 Schematic of an embedded MCM proposed by Johnson et al. [3].

Source: Reproduced with permission of IEEE.

The chips are interconnected with planar thin film process steps. An additional metallization layer is used for the interconnection to the next packaging hierarchy. The cavity is etched anisotropically into a silicon wafer using standard MEMS technology, which gives 54.74° sidewall angles. A 15 μm thin Si membrane was left to facilitate the deposition of the metal routing on the top Si surface. This membrane was removed by dry etching before chip embedding. The components are inserted from the backside and glued inside the thermally oxidized Si carrier with an adhesive (epoxy resin with 75% inorganic filler). In one of these first embedding approaches, benzocyclobutene (BCB) was deposited on top of the Si wafer containing four ICs for planarizing the surface of the substrate for the subsequent routing process. The low curing temperature is of great benefit for this embedding‐type approach due to the low thermal stability of the epoxy resin used for gap filling. After curing the BCB was structured by reactive ion etching (RIE). To correct for chip‐to‐wafer misalignment occurring during die mounting from the backside of the substrate, a computer program was written that automatically calculated a corrected pattern generator file for mask making.

An even earlier approach for embedding was patented in 1968 by Ties Siebolt Te Velde and Albert Schmitz from Philips...

Table of contents

• Cover
• Table of Contents
• Preface
• List of Contributors
• Acknowledgments
• 1 History of Embedded and Fan‐Out Packaging Technology
• 2 FO‐WLP Market and Technology Trends
• 3 Embedded Wafer‐Level Ball Grid Array (eWLB) Packaging Technology Platform
• 4 Ultrathin 3D FO‐WLP eWLB‐PoP (Embedded Wafer‐Level Ball Grid Array‐Package‐on‐Package) Technology
• 5 NEPES’ Fan‐Out Packaging Technology from Single die, SiP to Panel‐Level Packaging
• 6 M‐Series™ Fan‐Out with Adaptive Patterning™
• 7 SWIFT® Semiconductor Packaging Technology
• 8 Embedded Silicon Fan‐Out (eSiFO®) Technology for Wafer‐Level System Integration
• 9 Embedding of Active and Passive Devices by Using an Embedded Interposer: The i2 Board Technology
• 10 Embedding of Power Electronic Components: The Smart p2 Pack Technology
• 11 Embedded Die in Substrate (Panel‐Level) Packaging Technology
• 12 Blade: A Chip‐First Embedded Technology for Power Packaging
• 13 The Role of Liquid Molding Compounds in the Success of Fan‐Out Wafer‐Level Packaging Technology
• 14 Advanced Dielectric Materials (Polyimides and Polybenzoxazoles) for Fan‐Out Wafer‐Level Packaging (FO‐WLP)
• 15 Enabling Low Temperature Cure Dielectrics for Advanced Wafer‐Level Packaging
• 16 The Role of Pick and Place in Fan‐Out Wafer‐Level Packaging
• 17 Process and Equipment for eWLB: Chip Embedding by Molding
• 18 Tools for Fan‐Out Wafer‐Level Package Processing
• 19 Equipment and Process for eWLB: Required PVD/Sputter Solutions
• 20 Excimer Laser Ablation for the Patterning of Ultra‐fine Routings
• 21 Temporary Carrier Technologies for eWLB and RDL‐First Fan‐Out Wafer‐Level Packages
• 22 Encapsulated Wafer‐Level Package Technology (eWLCSP): Robust WLCSP Reliability with Sidewall Protection
• 23 Embedded Multi‐die Interconnect Bridge (EMIB): A Localized, High Density, High Bandwidth Packaging Interconnect
• 24 Interconnection Technology Innovations in2.5D Integrated Electronic Systems
• Index
• End User License Agreement