Convergence of More Moore, More than Moore and Beyond Moore

Materials, Devices, and Nanosystems

Simon Deleonibus, Simon Deleonibus

• Verlag: Jenny Stanford Publishing
• Jahr: 2021
• ISBN:
  9781000064599
• Auflage: 1
• Thema: Physical Sciences
• Thema: Nanoscience

The era of Sustainable and Energy Efficient Nanoelectronics and Nanosystems has come. The research and development on Scalable and 3D integrated Diversified functions together with new computing architectures is in full swing. Besides data processing, data storage, new sensing modes and communication capabilities need the revision of process architecture to enable the Heterogeneous co integration of add-on devices with CMOS: the new defined functions and paradigms open the way to Augmented Nanosystems. The choices for future breakthroughs will request the study of new devices, circuits and computing architectures and to take new unexplored paths including as well new materials and integration schmes.

This book reviews in two sections, including seven chapters, essential modules to build Diversified Nanosystems based on Nanoelectronics and finally how they pave the way to the definition of Nanofunctions for Augmented Nanosystems.

Part I
FROM NANOELECTRONICS TO DIVERSIFIED NANOSYSTEMS

Chapter 1

The Era of Sustainable and Energy Efficient Nanoelectronics and Nanosystems

Simon Deleonibus

Université Grenoble Alpes, CEA-Leti, MINATEC Campus, Grenoble, France

[email protected]

Major power consumption reduction will drive the design of future integrated circuit technologies and architectures. They will consequently request less energy greedy devices and interconnect systems. To meet new societal needs, the electronic market will embrace a continuous growth, accompanied by the feasibility of autonomous and mobile systems. Since its beginning, the linear scaling of complementary metal oxide semiconductor (CMOS) devices has met many hurdles, requesting new process modules, for the sake of their energy efficiency maximization. This chapter presents the solutions to integrate thin film-based devices, necessary to the design of architectures and systems capable of facing these challenges at the sub-10 nm node level. Fabricating circuits with increasing complexity in high volume will appeal for zero intrinsic variability, as well as three-dimensional (3D) integration of hybrid, heterogeneous technologies at the device, functional, and system levels. The maximization of energy efficiency of cointegrated low power and high performance logic, memory, and nanosystem devices will significantly impact the world energy-saving balance. The future of nanoelectronics will need to be energy and variability efficiency (EVE) conscious. On another aspect, scarcity of materials can have a serious impact on the feasibility of our future devices and systems. In order to prevent such a situation, the implementation of new process technologies, such as catalysis, or material recycling through circular economy may show the way to virtuous solutions.

1.1 Introduction

Section 1.2, Energy and Variability Efficient Nanoelectronics, describes the major hurdles and limits that occur while increasing silicon CMOS technology density, either by geometrical scaling or by exploiting the third dimension. Because devices and interconnect dimensions approach the molecular size, zero intrinsic variability becomes a serious question. How long will Moore’s law be conditioning technological progress? Such a question is different from the question of linear scaling of devices, thanks to the advent of 3D integration. Section 1.3, More Moore and More Than Moore Cointegrated into 3D Zero Power Systems, describes the routes to introduce new functions and applications by mixing the worlds of logic, memory, and devices for diversification. New opportunities will appear to introduce low-dimensionality materials, activate the pervasiveness of technologies, and develop multiphysics modeling in a massive way. The More Moore, More Than Moore, and Beyond Moore worlds will then meet for 3D integration to propose new computing architectures and advanced autonomous systems consuming zero power from an electric grid in a sustainable mode.

1.2 Energy and Variability Efficient Nanoelectronics

1.2.1 Moore’s Law, More Than Moore, and Beyond Moore Challenges and Sustainability

It is very important to distinguish Moore’s law from individual device and geometrical scaling. Moore’s law was based on economic considerations regarding the historical trend on the multiplication by 2 every year of the number of devices “crammed on a chip” [1]. Such a statement automatically implies a reduction of the cost per function. Moore mentioned that the trend would be pursued in the future. At that time, bipolar transistors were the most advanced active devices of an integrated circuit. The microelectronics business had not adopted MOSFETs (metal oxide semiconductor field effect transistors) yet. MOSFET became popular around 1970 [2] while beliefs predicted its fading progress by the end of the 1970s! Actually, no geometrical scaling rule of MOSFET was clearly established before Dennard et al.’s work [3] on scaling, taking advantage of self-aligning source and drain doping by ion implantation on a polysilicon gate.

The historical trend had been followed naturally until the beginning of the 1990s. The evolution was agreed to be sustainable, when the US National and the International Technology Roadmap for Semiconductors (ITRS) edited the first coordinated roadmaps. The semiconductor equipment suppliers and end users requested integrated device manufacturers to “sit around a table” and discuss about objectives, well documented and realistic roadmaps [4, 5] (Fig. 1.1). It took a while to select the good benchmarkers while microelectronics kept gaining in maturity. The main guideline approved by the roadmap working groups was the geometrical scaling of CMOS and memories based on the MOSFET technology [6]. Bipolar devices, associated with CMOS in BiCMOS schemes, were still dominating in the RF (radio frequency) business. Thanks to the success of MOSFET technology, the number of transistors in dynamic memories and microprocessor circuits surpassed 1 billion as early as 1995 [7] and 2006 [8], respectively. CMOS scaling is based on a list of geometrical rules that establish, in fine, the resulting electrical characteristics, power consumption, and performance of devices. The ITRS identified three main families of devices, linked to the major categories of products that the industry would be delivering: high performance (HP), low operating power (LOP), and low standby power (LSTP) device architectures were defined. Meanwhile, three domains were defined by the European MEDEA initiative, depending on their maturity, pervasiveness, specificity to applications, or aptitude to scaling: they first defined the domains more Moore and more than Moore, which distinguished, respectively, CMOS (linearly scalable) and the devices that were more application oriented and likely to improve the diversification of integrated circuits and systems. The more than Moore devices domain defines a category including sensors and actuators, memories, RF devices and passives, power/high voltage devices, bioelectronic devices, and so on [4] (Fig. 1.2). In parallel, various types of devices that could challenge CMOS either in their ultimate configuration or by using a state variable different from electric charge have been investigated. The so-called Beyond CMOS or Beyond Moore domain lists the features of these devices by systematically benchmarking their progress or maturity year after year. After gaining in maturity, some of them might enter a transition table before being considered for the roadmap. That was the case for FinFET or multigate devices before their introduction into the roadmap tables. Magnetic random-access memories (MRAMs) and particularly ...