Atomic Layer Processing

Semiconductor Dry Etching Technology

Thorsten Lill

• Verlag: Wiley-VCH
• Jahr: 2021
• ISBN:
  9783527824205
• Auflage: 1
• Thema: Technology & Engineering
• Thema: Materials Science

Learn about fundamental and advanced topics in etching with this practical guide

Atomic Layer Processing: Semiconductor Dry Etching Technology delivers a hands-on, one-stop resource for understanding etching technologies and their applications. The distinguished scientist, executive, and author offers readers in-depth information on the various etching technologies used in the semiconductor industry, including thermal, isotropic atomic layer, radical, ion-assisted, and reactive ion etching.

The book begins with a brief history of etching technology and the role ithas played in the information technology revolution, along with a collection of commonly used terminology in the industry. It then moves on to discuss a variety of different etching techniques, before concluding with discussions of the fundamentals of etching reactor design and newly emerging topics in the fieldsuch asthe role played by artificial intelligence in the technology.

Atomic Layer Processing includes a wide variety of other topics as well, all of which contribute to the author's goal of providing the reader with an atomic-level understanding of dry etching technology sufficient to develop specific solutions for existing and emerging semiconductor technologies. Readers will benefit from:

• A complete discussion of the fundamentals of how to remove atoms from various surfaces
• An examination of emerging etching technologies, including laser and electron beam assisted etching
• A treatment of process control in etching technology and the role played by artificial intelligence
• Analyses of a wide variety of etching methods, including thermal or vapor etching, isotropic atomic layer etching, radical etching, directional atomic layer etching, and more

Perfect for materials scientists, semiconductor physicists, and surface chemists, Atomic Layer Processing will also earn a place in the libraries of engineering scientists in industry and academia, as well as anyone involved with the manufacture of semiconductor technology. The author's close involvement with corporate research & development and academic research allows the book to offer a uniquely multifaceted approach to the subject.

1
Introduction

People have been scratching, engraving, and carving stone, wood, bones, and other materials since the dawn of time to record information and to create art. These early forms of material removal can possibly be viewed as the origins of etching technology.

The importance of etching throughout history can be illustrated with a few remarkable examples. Hammurabi’s code of law was inscribed into a stone stele at around 1754 BCE and is one of the earliest and influential legal tests. Carved woodblocks were applied to print paper money during the Tang dynasty in China during the second half of the first millennium CE. Michelangelo’s statue of David is an embodiment of the European renaissance. All these etching techniques use physical energy to remove material.

Chemical etching techniques using acids evolved in medieval Europe to decorate armor with greater detail. Selected areas of a surface were covered by soft “maskants,” which could be easily removed with sharp objects and the exposed areas were removed by “etchants.” One of the greatest etchers of all times was Rembrandt who created around 290 prints. Many of his etching plates still survive.

John Senebier discovered in 1782 that certain resins lost their solubility to turpentine after exposure to light. This allowed to create early forms of photomasks and ultimately led to the development of photographic methods. Paul Eisler invented the printed and etched circuit board in 1936. Etching was also instrumental for the realization of the first integrated circuits by Jack Kilby and Robert Noyce in 1958. The words “etch” and “etching” figure 11 times in Kilby’s seminal US patent 3 138 743 “Miniaturized electronic circuits” (Kilby 1959).

Originally, integrated circuits were etched with wet chemical methods using photoresists as a mask. While these methods can be directional for some single crystal materials and selected etchants, removal of amorphous materials etch proceeds in all directions roughly with the same rate. This kind of etching is also called isotropic. It works only for features where the lateral dimension is much larger than the thickness of the material to be etched. This property is obviously an obstacle for device shrinking. Another drawback of wet etching is the creation of large amounts of toxic waste.

To overcome these challenges, dry plasma etching methods were introduced into the manufacturing of integrated semiconductor devices in the 1980s. When a plasma is in contact with a solid surface a phenomenon called sputtering occurs, which causes material removal. Sputtering was discovered by W.R. Grove in 1852. Physical sputtering with noble gas plasmas was used in the 1960s in the electronics industry. When the wafer is placed on a radio frequency (RF) powered electrode, ions are accelerated, and the sputter rate can be increased to make the method more productive (Coburn and Kay 1972). However, physical sputtering is still too slow to be useful in the manufacturing of semiconductor devices. It also critically lacks the selectivity to mask and stop materials.

Chemistry provided the necessary performance boost. The development of chemical plasma etching started with stripping of photoresists in oxygen RF plasmas (Irving et al. 1971). Soon, fluorine and chlorine plasma were tested to etch a wide range of materials. An increase of the silicon etching rate by a factor of 10–20 was observed when replacing argon with fluoro‐chloro‐hydrocarbon gases (Hosokawa et al. 1974). The term “reactive ion etching” (RIE) was coined in the mid 1970s for etching technologies involving chemically reactive plasmas where the wafer is placed on an RF‐powered electrode. Initially, the mechanism of the etch rate enhancement was not understood even though the benefits were clearly demonstrated in experiments (Bondur 1976). Coburn and Winters found that “the magnitude of the etch rates which are observed are such that the enhancement caused by ion bombardment cannot be easily explained by simply superimposing a physical sputtering process onto the chemical etching process” (Coburn and Winters 1979). Their seminal experiments demonstrated the existence of synergy between the ion and neutral fluxes. Synergy is also a key concept in atomic layer etching (ALE) with atomic layer fidelity. We will use this concept throughout this book.

Production‐worthy etching reactors took hold in the semiconductor industry with the introduction of batch RIE reactors based on developments at Bell Labs. An overview of the evolution plasma etching equipment can be found in a review article by Donnelly and Kornblit (2013). The 1990s saw the introduction of single wafer etching reactors, which improved wafer to wafer repeatability and overall process control. This decade was also the time of search for the best source technology for the large number of rapidly emerging applications. The first single wafer etching reactors were simple parallel plate reactors with RF power applied to the wafer pedestal. Some embodiments featured etch rate enhancing magnetic fields.

High‐density plasmas powered by transformer‐coupled plasma (TCP) or inductively coupled plasma (ICP) established themselves as the tools of choice for silicon and metal etching. Medium‐density capacitively coupled plasma (CCP) sources proved superior for etching of silicon oxide and other dielectric materials. CCP reactors found widespread application with the introduction of damascene metallization in the end of the 1990s, which created a large market for etching of materials with low relative dielectric constant, the so‐called low‐k materials.

The 2000s were the decade of continuous improvement of uniformity across the wafer by means of radial uniformity tuning knobs for ion flux, neutral flux, and temperature. This was driven by the transition from 200 to 300 mm wafers and escalating uniformity requirements to satisfy Moore’s Law. The last decade was characterized by a strong focus on within die and feature scale performance. This is caused by the transition from traditional Moore’s Law scaling to vertical device scaling, which drives devices with increasingly high aspect ratios such as 3D NAND flash and fin field effect transistors (FinFET’s).

One of the solutions to within die performance challenges is “time domain processing,” for instance plasma pulsing, and mixed mode pulsing (MMP) where RF power and gas flows are pulsed. Time domain processing necessitates that all subsystems operate repeatably on second timescales and faster. This is an enormous engineering challenge considering all the parameters that need to be controlled with the large number of process parameters including the radial tuning knobs. Model‐based process controllers and machine learning process development algorithms are being introduced.

As semiconductor devices are shrinking to sub‐10 nm dimension, etching technologies with atomic‐scale fidelity are required. Here fidelity refers to the degree of matching to the intent of design engineers in shape and composition (Kanarik et al. 2015). ALE, which has been studied in laboratories for 30 years, promises to deliver this level of performance. The first report on ALE was published in Yoder’s US patent 4 756 794 entitled “Atomic layer etching” (Yoder 1988). After a first wave of research during the 1990s, a second wave of interest and development started in the mid‐2000s driven by the need for etching technologies with infinite selectivity and the ability to remove controlled amounts of material down to sub‐monolayer resolution.

A variety of etching technologies were discussed under the umbrella of “ALE” including very slow RIE processes, radical and vapor etching. This lack of common understanding and terminology in the etching community slowed the development of true ALE. A definition of ALE as an etching process comprising of at least two self‐limited steps was adopted during a Sematech workshop on ALE in April 2014. This definition is in analogy to its counterpart of atomic layer deposition (ALD). Many of the established concepts in ALD were adopted in ALE. The separation of the etching process into self‐limiting steps breaks the trade‐offs caused in RIE by simultaneous ion and neutral fluxes. The result is improved uniformity across the wafer, across features with different critical dimension called aspect ratio dependent etching (ARDE), and surface smoothness (Kanarik et al. 2015). It also greatly simplifies the process and makes ALE accessible to a rigorous fundamental understanding.

This book covers the latest research and developments of directional and isotropic ALE and puts them into the context of established dry etching technologies for semiconductor devices. In this book, we will introduce etching technologies in the order of increasing complexity. We will begin with critical elementary surface processes, followed by single species etching technologies (thermal etching and radical etching), sequential multi‐species etching (ALE), and multi‐species continuous processing (RIE). Finally, we will review plasmas and other methods to produce the species we discussed in the first half of the book.

This structure does not consider the chronological order of discovery or the size of the market of the various etching technologies. Novel ALE will be studied before classical RIE. Directional ALE is introduced as a simplified embodiment of RIE, which is amiable to a rigorous treatment. Salient RIE properties will be presented as the result of a lack of self‐limitation of continuous processing where all species fluxes are on all the time. The goal is to understand RIE on an atomic level as rigorously as possible to illuminate the “black box” that RIE still is today (Winters et al. 1977; Gottscho et al. 1999).

Specific etching applications such as gate etching, contact etching, or 3D NAND channel hole etching will be introduced as examples for the mechanisms discussed without attempting to give a comprehensive description of the process challenges and solutions. The emergence and evolution of semiconductor devices and the corresponding etching applications is simply too fast paced, and such an attempt would be outdated within a few years. Rather, the intend of this book is to provide an atomic level understanding of all dry etching technologies, which will hopefully help to develop specific solutions for existing and emerging semiconductor devices.

Plasmas are the method of choice to generate ions and radicals used in dry etching. In this book, the plasma and source technologies are covered to a level of detail sufficient enough to understand how they impact the species fluxes to the etching surface. For deeper understanding, we refer to the semi...