Radiation Effects in Semiconductors

Krzysztof Iniewski, Krzysztof Iniewski

• Éditeur: CRC Press
• Année: 2018
• ISBN:
  9781351833752
• Édition: 1
• Sujet: Technology & Engineering
• Sous-sujet: Electrical Engineering & Telecommunications

Space applications, nuclear physics, military operations, medical imaging, and especially electronics (modern silicon processing) are obvious fields in which radiation damage can have serious consequences, i.e., degradation of MOS devices and circuits. Zeroing in on vital aspects of this broad and complex topic, Radiation Effects in Semiconductors addresses the ever-growing need for a clear understanding of radiation effects on semiconductor devices and circuits to combat potential damage it can cause.

Features a chapter authored by renowned radiation authority Lawrence T. Clark on Radiation Hardened by Design SRAM Strategies for TID and SEE Mitigation

This book analyzes the radiation problem, focusing on the most important aspects required for comprehending the degrading effects observed in semiconductor devices, circuits, and systems when they are irradiated. It explores how radiation interacts with solid materials, providing a detailed analysis of three ways this occurs: Photoelectric effect, Compton effect, and creation of electron-positron pairs. The author explains that the probability of these three effects occurring depends on the energy of the incident photon and the atomic number of the target. The book also discusses the effects that photons can have on matter—in terms of ionization effects and nuclear displacement

Written for post-graduate researchers, semiconductor engineers, and nuclear and space engineers with some electronics background, this carefully constructed reference explains how ionizing radiation is creating damage in semiconducting devices and circuits and systems—and how that damage can be avoided in areas such as military/space missions, nuclear applications, plasma damage, and X-ray-based techniques. It features top-notch international experts in industry and academia who address emerging detector technologies, circuit design techniques, new materials, and innovative system approaches.

Section II

Circuits and Systems

7 Radiation Hardened by Design SRAM Strategies for TID and SEE Mitigation

Lawrence T. Clark

CONTENTS

7.1 Chapter Overview

7.1.1 Embedded SRAMs in Integrated Circuit Design

7.1.2 The Radiation Space Environment and Effects

7.1.3 Chapter Outline

7.2 Radiation Hardening

7.2.1 Total Ionizing Dose Effects

7.2.2 Single-Event Effects in SRAMs

7.3 Radiation Hardening by Design in SRAMs

7.3.1 SRAM Cell Read and Write Margins

7.3.2 Reverse-Body Bias

7.3.3 RHBD SRAM Cell Design

7.3.3.1 Conventional Two-Edged Transistor Cell (Type 1)

7.3.3.2 Annular NMOS Based SRAM Cell (Type 2)

7.3.3.3 PMOS Access Transistor SRAM Cell (Type 3)

7.3.3.4 Two-Edged NMOS Access Transistor SRAM Cell with Annular Pull-Down Transistors (Type 4)

7.4 SNM Test Structure

7.5 Experimental TID Testing Results

7.5.1 Impact of V_DD Bias on TID Response

7.5.2 Impact of TID on Cell Margins

7.5.3 Type 4 Cell

7.5.4 Type 1 Cell with RBB—Array Design Considerations

7.5.5 Type 1 Cell with RBB—Transistor Level Measurements

7.5.6 Test SRAM Designs and Experiments

7.5.7 Type 1 Cell with RBB—SRAM Measurements

7.5.8 90 nm Transistor-Level Response

7.6 Single-Event Effects in Unhardened SRAM

7.7 Single-Event Effects Mitigation

7.7.1 130 nm SRAM Design with RBB + SC Support and SEE Mitigation

7.7.2 SRAM Column Circuits

7.7.3 SRAM Operation with RBB + SC

7.7.4 Experimental SEE Measurements

7.8 Summary and Conclusions

References

7.1 CHAPTER OVERVIEW

7.1.1 EMBEDDED SRAMS IN INTEGRATED CIRCUIT DESIGN

Static random access memory (SRAM) is ubiquitous in modern system-on-a-chip (SOC) integrated circuits (ICs). Due to its value in programmable systems by providing fast scratchpad memory in embedded and real-time applications as well as space for large working sets in microprocessor designs, IC SRAM content continues to grow. As ICs surpass 1 billion transistors, and given the high relative design and power efficiency of memory arrays compared with random logic, SRAM is projected to comprise 90% of the total die area by 2013 [1]. For instance, the Itanium processor has progressed from 6 MB and 9 MB L3 caches on 130 nm fabrication processes to 24 MB caches on the 65 nm technology generation [2–4]. The Xeon processors include 16 MB caches [5]. Consequently, ICs designed for space and other radiation environments require robust SRAM designs if they are to track the size and performance of commercial ICs.

7.1.2 THE RADIATION SPACE ENVIRONMENT AND EFFECTS

The earth’s radiation environment consists of electrons, protons, and heavy ions. The former two are trapped by the earth’s magnetic field where they follow the field lines, where these particle fluxes are highest. A total of 85% of galactic cosmic ray particles are protons, with the rest composed of heavy ions [6]. Cosmic ray flux is essentially omnidirectional, so microelectronics may be affected by particles impinging at any angle. Importantly, this means that ions can transit an IC parallel to the device surface, since there is no practical level of shielding that can stop all protons and heavy ions. Solar cycles also strongly affect the radiation environment. Ordinarily the helium ions in the solar emitted particle fluxes comprise 5–10%, and heavier ion fluxes are very small, well below the galactic background. During major solar events, some heavy-ion fluxes may increase by up to four orders of magnitude above the galactic background, for as long as days at a time.

The dominant radiation effects on microcircuits in space are due to deposited charge from ionization tracks produced by single particles. These produce two primary effects. First, collected charge from a single particle can upset circuit state, referred to as a single-event effect (SEE). Second, changes in the charge state of dielectrics due to total accumulated ionization can alter device characteristics, referred to as total ionizing dose (TID) effects [7].

Both protons and heavy ions can deposit charge that can upset the circuit state. Upsetting a feedback (state storage) node such as a memory bit is defined as a single-event upset (SEU). Heavy ions affect the circuit state through direct ionization due to columbic interaction with the substrate material, producing about 10 fC of charge per Lm of track length per linear energy transfer (LET). Memory cells are often characterized for SEU by the total charge Q_crit that is required to upset their state. Charge that temporarily disrupts a logic node results in an incorrect voltage transient of a magnitude and duration determined by the node capacitance and the driving circuit’s ability to remove the charge. These are referred to as a single-event transient (SET). An SET can affect the IC architectural state (the state that is visible to the surrounding system) only if sampled by a latch whose output is subsequently used.

Protons interact with the silicon through multiple mechanisms, predominantly by direct ionization but also through secondary nuclear particle emission due to Si recoil. The former generates relatively small amounts of charge, but the latter can upset circuits hardened to high LET. Approximately 1 in 100,000 protons impinging will produce a nuclear reaction. Moreover, the multiple secondary particles may interact with the circuit after moving in multiple directions. A single particle produces charge in linear tracks. Charge is collected by diffusion and by drift, with the latter due to the device depletion regions. Charge collection is enhanced by “funneling,” which is a third field driven collection mechanism that extends the field driven collection by the redistribution of the deposited carriers. Parasitic bipolar action can also increase the current collected at a specific node, greatly increasing the upset rate and extent.

Impinging particles can also permanently disable the microcircuit by excessive displacement damage or by rupturing the gates. Such permanent effects are not pertinent to the discussions in this chapter.

7.1.3 CHAPTER OUTLINE

This chapter focuses on SRAM design using radiation-hardening-by-design (RHBD) techniques. Both TID and SEE hardening are covered. The latter approaches described assume that error detection and correction (EDAC) is used to mitigate individual SEU, as RHBD hardened cell approaches have diminishing value in modern highly scaled fabrication processes. Small, dense geometries make simultaneous upset of multiple circuit nodes from a single particle strike increasingly likely. A primary focus, therefore, is on mitigating SETs that can cause upsets that confound the EDAC or otherwise cause incorrect SRAM operation. All of the approaches examined in this chapter have been fabricated and tested—measurements quantifying their effectiveness are also described and discussed.

The last section briefly outlined the space radiation environment. Subsequent sections include a discussion of basic SRAM cell design, which is tutorial in...