Computer Science
D Type Flip Flops
D type flip-flops are fundamental building blocks in digital circuits. They are capable of storing a single bit of data and are commonly used for sequential logic operations. The state of a D type flip-flop is determined by its input and clock signal, making it useful for applications such as data storage, synchronization, and control in computer systems.
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10 Key excerpts on "D Type Flip Flops"
eBook - PDF- B. Holdsworth(Author)
- 2014(Publication Date)
- Butterworth-Heinemann(Publisher)
5 Single-bit memory elements 5.1 Introduction A digital logic circuit is usually made up of combinational elements such as NAND and NOR gates and memory elements which might be single bit memory elements such as discrete flip-flops or, alternatively, an array of flip-flops such as might be found in a shift register. With the introduction of memory elements as components in digital circuits, an additional variable, time, has been introduced and must be taken into account when dealing with digital circuit problems. In effect, logic operations can now be performed sequentially, information being stored in a memory element and being released at some particular instant so that it can take part in a controlled combinational operation. Circuits operating in this way are called sequential circuits. Some sequential circuits are controlled by a repetitive clock signal, in which case the circuit is called a synchronous or, alternatively, a clock-driven circuit. Other sequential circuits are controlled by random events in which case they are called asynchronous or event-driven circuits. The basic characteristic of any flip-flop is that it has two stable states which can be represented by logical Ό' or logical 'Γ respectively. There are a number of flip-flops in common usage in digital circuits. They are called T, SR, JK and D type flip-flop. This chapter is concerned with the logical behaviour of these various types of flip-flop. 5.2 The T flip-flop This flip-flop is conventionally represented by the diagram shown in figure 5Λ{α). The device has one input Tand complementary outputs ßandß. 91 92 Single-bit memory elements la) 0 T »»I _ I o 0*0 ' f T 0 = 1 (CO T3&-C—j&J^®)— ' (e) Present state Γ ' 0 0 1 1 0> 0 1 0 1 Next 1 state Q**t 1 0 1 1 0 (
eBook - PDF- B. Holdsworth(Author)
- 2013(Publication Date)
- Butterworth-Heinemann(Publisher)
For this D-type flip-flop there is one input or data line D and two complementary output lines, Q and Q. The two stable_states are defined as (a) Q = 0 and Q = 1, and (b) Q = 1 and Q = 0. Control of the transfer of data D to the output Q line is achieved via the clock line. The logical behaviour of the D-type flip-flop is defined by the state table shown in Figure 2.9(e). In the first two columns of this |Ck Q Present Next • state state Q D f 0 / Q f + 5 ' 0 0 0 0 1 0 1 0 1 1 1 1 («) (b) Figure 2.9 (a) The D-type flip-flop (b) Truth table 36 Logic table every possible combination of the present input D' and the present output Q' are tabulated. The last column gives the resulting next state of the flip-flop Q' + ô '. From the state table the following equation is obtained: Q'+°' = (DQ + DQ)' or Q'+ 6 ' = D' This is called the characteristic equation of the flip-flop and it indicates that the next state of the output Q t+bt is identical to the present state of the input data D*. 2.7 The edge-triggered D-type flip-flop This device can be regarded as one that transfers data at the D-input to the Q-output. Such a transfer is initiated by a clock signal, which may be regarded as an enabling signal that allows the transfer to take place. A typical example of a clock signal is shown in Figure 2.10. Transfer of data normally takes place on either the leading or trailing edge of a clock pulse. It should be noticed that there can be no change of the Q output when the clock is low. This period is referred to as the asynchronous period of the clock signal and, in effect, during this period the flip-flop is disabled. Leading edge (+ve transition) fL Trailing edge (-ve transition) Figure 2.10 Typical clock wavform A flip-flop that changes its state on a clock transition is called an edge-triggered flip-flop. The sensitivity of the flip-flop to a clock transition is indicated by > at the clock input.
eBook - PDF- R. M. Marston(Author)
- 2013(Publication Date)
- Newnes(Publisher)
4 Clocked flip-flops and counters Most digital ICs can be classified into either of two basic types; the first is those based on simple logic gate networks, and many of these have already been described in particular, Chapter 2. The second type is those based on 'clocked' bistable or flip-flop elements, and this group includes simple counter/divider ICs, shift registers, data latches, and complex ICs such as presettable up/down counters, etc. This chapter takes a detailed look at clocked flip-flop basics, and pre-sents practical user information on a variety of popular TTL clocked flip-flop and counter/divider ICs. Clocked flip-flop basics One of the simplest types of digital flip-flop circuit is the cross-coupled NOR-type bistable. This flip-flop has already been briefly described in Chapter 3, but its basic circuit and standard symbol are repeated here in Figure 4.1 , together with its full Truth Table. The circuit's basic action is such that its Q output switches to logic-1 (and NOT-Q goes to logic-0) when the SET terminal is taken to logic-1, T -n RESET J 'JI Q r-» (b) S R Q 5 0 0 no change 0 1 0 1 1 0 1 0 1 1 0 0 (disallowed) (c) Figure 4.1 Circuit (a), symbol (b), and Truth Table of the NOR-type S-R flip-flop. 110 Modern TTL Circuits and then latches into that state even if SET and RESET are both then pulled to logic-0. The only way that the latched output states can be changed is to apply a logic-1 to the RESET terminal, in which case the Q output switches to logic-0 and latches into that state even if SET and RESET are both then pulled to logic-0. The basic SET-RESET (S-R, or R-S) flip-flop thus acts as a simple memory element that 'remembers* which of the two inputs last went to logic-1. Note that if both inputs go to logic-1 simultaneously, both outputs go to logic-0, but if both inputs then simultaneously switch to logic-0 the output states cannot be predicted; the 'both inputs high' con-dition is thus regarded as a 'disallowed' state.
eBook - PDF- R. Townsend(Author)
- 2014(Publication Date)
- Butterworth-Heinemann(Publisher)
The flip-flops may be set to either the 1 or 0 state and are provided with addressing logic on the chip so that only selected flip-flops are set or reset. Essentially the whole operation of a computer system can be reduced to a problem of transferring digital information from one register to another, usually by way of more or less complicated interacting logic. The Flip-Flop Register To the computer designer, the flip-flop now usually arrives ready made as an integrated circuit, or indeed there may be a number of flip-flops 28 Counters and Sequential Grcuits 29 ■CH Input CH Output -CH Figure 3.1 with inter-connecting logic designed to perform some predetermined function. The logic symbol for a SET-RESET flip-flop is shown in Figure 3.1. Usually each flip-flop has a name symbol which is often an abbreviation of its function, for example CH (short for CHECK), and the outputs which are in both true and complement form have the same name. The symbol might also have a number representing a bit number in a register or counter. The simplest flip-flop can be made from 2-NAND circuits as shown in Figure 3.2. The digital inputs can be at Figure 3.2 one of two levels, representing 1 or 0, which will also be called, high and low. Remembering that with the NAND circuit the output is low only when both of its inputs are high. Suppose that both X and Y are high. The circuit must then have 2 stable states and will settle with either Q high and Q low or vice versa. If we make the input X or Y low to the conducting NAND circuit i.e. with a low output, its output must become high, causing the opposite NAND to be put into the conducting state, and thus reversing the state of the flip-flop. If it is wished to set or reset the flip-flop at only a given time we can gate the S (set) or R (reset) inputs with a pulse that enables the flip-flop only when needed as shown in Figure 3.3.
eBook - PDF- R M MARSTON(Author)
- 1995(Publication Date)
- Newnes(Publisher)
A far more versatile device is the 'data' or D-type flip-flop, which is made by connecting the clocked master-slave flip-flop in the configuration shown in Figure 7.5. Here, an inverter is wired between the Sand R terminals of the flip-flop, so that these terminals are always in anti-phase, and the input data is Clocked flip-flops 147 CLOCK (a) (b) Figure 7.4 A clocked ltoggle' or IT-type' flip-flop is constructed as shown in (a), and uses the standard symbol of (b) DATA .----.1 ClOCK~-- £t a eLK Q 0 eLK Q Q 0 .s-o 1 1 .r' 1 0 ~) ~) Figure 7.5 Basic circuit (a), symbol (b), and truth table of the D-type flip-flop DATA£tDATA IN 0 Q OUT CLOCK elK Q (a) CLOCK (f) cix (b) OUT ( f12) Figure 7.6 A D-type flip-flop can be used as (a) a data latch or (b) a divide-by-2(binary counter/divider) circuit J CLOCK~I'----'l~-'----I K -------(a) J K ClocIdng Adlon 0 0 Does nothing (inhibits) 0 1 sets Q output low 1 0 seea Q output high 1 1 Changes output state {j a eLK K is (b) (c) Figure 7.7 Basic circuit (a), symbol (b), and action table of the JK flip-flop applied via a single data pin. Figures 7.5(b) and 7.5(c) show the symbol and truth table of the D-type flip-flop, which can be used as a data latch by using the connections shown in Figure 7.6(a), or as a binary counter/divider by using the connections shown in Figure 7.6(b) (with the D and not-Q terminals coupled together). Figure 7.7 shows the basic circuit, symbol and action table of an even more 148 Clocked flip-flops FF1 (a) CLOCKED INPUTS D ClK Q Q o I 0 1 1 I 1 0 Q I Changes DIRECT INPUTS R S Q Q 0 0 Clocked operation 0 1 1 0 1 0 0 1 1 1 Disallowed (b) Figure 7.8 Functional diagram (a) and truth tables (b) of the 40138 dual D-type flip-flop IC important and versatile clocked flip-flop, which is universally known as the JK-type flip-flop. This flip-flop can be 'programmed' to act as either a data latch, a counter/divider, or a do-nothing element by suitably connecting the J and K terminals as indicated in the table.
eBook - PDFDigital Electronic Circuits
Principles and Practices
- Shuqin Lou, Chunling Yang(Authors)
- 2019(Publication Date)
- De Gruyter(Publisher)
5.2.4 Flip-flop conversion Generally, mainstream ICs of edge-triggered flip-flops are D flip-flop and J-K flip-flop. Other types of flip-flops can be implemented with D flip-flop and J-K flip-flop. The implementing method is to use characteristic equation of different types of flip-flops to determine the inputs of flip-flop. Example 5.5 Use a D flip-flop to construct a T ′ flip-flop. Solution The characteristic equation for D flip-flop is Q n + 1 = D . The characteristic equation for T ′ flip-flop is Q n + 1 = Q n . Compare the characteristic equation of two type of flip-flops, when D = Q n , a T ′ flip-flop can be constructed by using a D flip-flop. That is, a T ′ flip-flop can be implemented by connecting the Q output of D flip-flop with the D input. The logic diagram is shown in Figure 5.2.14(a). C D CP (a) (b) Q Q C D CP Q K J Q Figure 5.2.14: The logic diagram. CP 1 2 3 4 5 6 7 8 9 S d R d Q SET Toggle RESET Figure 5.2.13: Output waveform in Example 5.4. 5.2 Flip-flops 181 Example 5.6 Use a D flip-flop to construct a J-K flip-flop. Solution The characteristic equation for D flip-flop is Q n + 1 = D . The characteristic equation for J-K flip-flop is Q n + 1 = J Q n + KQ n . Compare the characteristic equation of two types of flip-flops, when D = J Q n + KQ n , a J-K flip-flop can be constructed by using a D flip-flop and few logic gates. The logic diagram is shown in Figure 5.2.14(b). 5.2.5 Flip-flop operating characteristics The operation characteristics for flip-flops includes the time for data receiving, state transition, propagation delay, or response. Generally, the specifications are applic-able to all CMOS and TTL flip-flops. Here, the D flip-flop is taken as an example to discuss the operating characteristics, as shown in Figure 5.2.15.
- Will Kimber(Author)
- 2016(Publication Date)
- Newnes(Publisher)
• The term delay flipflop describes what happens to the information (data) at the input D. This data arrives at the output Q following the application of one clock pulse and there is thus a one-bit time delay. • The advantage of the D flipflop over the RS flipflop is that the D-type has only one external data input, thus avoiding the indeterminate situation (R = S = 1) of the RS type. However, for the D flipflop, the situation where both preset and clear are logic 0 is naturally prohibited! The JK flipflop This is a versatile, widely used and universal flipflop, possessing the features of all the other types. The letters / and Κ have no literal meaning, but are compared to the RS flipflop, / with S (SET) and Κ with R (RESET). There is additional circuitry which prevents the JK flipflop being forced into the indeterminate state that occurs when S and R are both logic 1. It is a clocked flipflop which may also have a preset and clear input. The /, Κ and clock inputs are synchronous, whereas the preset and clear are asynchronous, that is, they can be applied at any time and will override any existing state. Figure 6.26 shows the circuit symbols for the JK flipflop. 106 Sequential systems 1: Flipflops Preset Preset -J Q *>Ck_ - Κ Q - J Q -->Ck_ - Κ Q-Clear Clear (a) (b) Figure 6.26 The JK flipflop: circuit symbols Practical Exercise 6.4 To investigate the action of the JK flipflop For this exercise you will need the following components and equipment: 1 - 74LS76 ic (dual JK flipflop with preset and clear active low, and negative edge triggering) 1 - 7LED (5 mm) and resistor (270 Ω) 1 - +5 V dc power supply 1 - pulse generator (1 kHz - see Figure 1.5) 1 - double beam cathode ray oscilloscope Figure 6.27 The JK flipflop: circuit for Practical Exercise 6.4 Procedure (a) 1 Connect up the circuit in Figure 6.27. The pin connection diagram for the 7476 is shown in Figure 6.28.
- Charles Roth, Jr., Larry Kinney, Eugene John, , Charles Roth, Jr., Larry Kinney, Eugene John(Authors)
- 2020(Publication Date)
- Cengage Learning EMEA(Publisher)
For correct operation an asynchronous circuit must not contain any critical races. 11.10 Summary In this unit, we have studied several types of latches and flip-flops. Flip-flops have a clock input, and the output changes only in response to a rising or falling edge of the clock. All of these devices have two output states: Q = 0 and Q = 1. For the S-R latch, S = 1 sets Q to 1, and R = 1 resets Q to 0. S = R = 1 is not allowed. The S-R flip-flop is similar except that Q only changes after the active edge of the clock. The gated D latch transmits D to the Q output when G = 1. When G is 0, the cur- rent value of D is stored in the latch and Q does not change. For the D flip-flop, Q is set equal to D after the active clock edge. The D-CE flip-flop works the same way, except the clock is only enabled when CE = 1. The J-K flip-flop is similar to the S-R flip-flop in that when J = 1 the active clock edge sets Q to 1, and when K = 1, the active edge resets Q to 0. When J = K = 1, the active clock edge causes Q to change state. The T flip-flop changes state on the active clock edge when T = 1; otherwise, Q does not change. Flip-flops can have asynchronous clear and preset inputs that cause Q to be cleared to 0 or preset to 1 independently of the clock. Flip-flops can be constructed using gate circuits with feedback. Analysis of such circuits can be accomplished by tracing signal changes through the gates. Analysis can also be done using flow tables and asynchronous sequential circuit theory, but that is beyond the scope of this text. Timing diagrams are helpful in understanding the time relationships between the input and output signals for a latch or flip-flops. In general, the inputs must be applied a specified time before the active clock edge (the setup time), and they must be held constant a specified time after the active edge (the hold time). The time after the active clock edge before Q changes is the propagation delay.
eBook - PDF- J Kraft(Author)
- 2013(Publication Date)
- Future Managers(Publisher)
98 Module 4 • Memory Elements and Flip-Flops (Latches) This type of flip-flop has a great advantage in that no un-permissible logic combinations can be applied to the input of the flip-flop. Figure 4.25 (a), (b) and (c) illustrates this type of circuit where (a) is the circuit diagram, (b) is the IEC-symbol and (c) is the truth table. & & & & 1 & & & & 1 9 7 6 5 4 3 2 8 Q _ Q RD SD T (a) Master Slave K J _ Q Q RD SD (b) CL J K K Q (c) _ Q not Q n Q n J not Q n Q n 0 0 0 0 0 0 1 1 1 1 1 1 Figure 4.25 The operation of the circuit can be described briefly as follows. J = 0 and K = 0 The output will remain unchanged when the clock pulse is applied. J = 1 and K = 0 The circuit will be reset since a 0 will be carried over to the output when the clock pulse is applied. J = 0 and K = 1 The circuit will be set since a 1 will be carried over to the output when the clock pulse is applied. J = 1 and K = 1 In this instance the circuit will behave in the same manner as a T flip-flop and the output will switch over or toggle to the opposite position with every clock pulse applied. 99 N3 Logic Systems | Hands On! The timing diagram for a JK master-slave flip-flop is illustrated in figure 4.26. CL 1 8 7 6 5 4 3 2 Q K J Figure 4.26 Having discussed the four types of master-slave flip-flops a summary is given below on how to modify or change the flip-flops from one type to another. These modifications or changes will take a JK master-slave flip-flop and indicate the changes which need to be made. To obtain an RS master-slave flip-flop, modify a JK master-slave flip-flop and replace the J with S and replace the K with R. (see figure 4.18 (a)). To obtain a D master-slave flip-flop, modify an RS master-slave flip-flop by placing an inverter between R and S. (see figure 4.20 (a)). To obtain a T master-slave flip-flop, the J and K of a JK master-slave flip-flop are kept at logic 1.
eBook - PDFComputers and Microprocessors
Made Simple
- George H. Olsen, Ian Burdess(Authors)
- 2016(Publication Date)
- Made Simple(Publisher)
These systems, which in their own right are as important as the combinational logic circuits, are known as sequential logic circuits. The main feature of sequential systems is that they require some form of memory which is capable of remembering the last state in which the circuit was set. They must also incorporate feedback so that the response of the system Digital Computers 97 to an input change can be a function of the state of the circuit prior to this change. The most basic of the systems in this group is known as the set reset (or SR) flip-flop, the symbol of which, with its NAND gate equivalent, is shown in Fig. 77. The feedback may be seen in the logic block diagram for the device, in the connection from the output of gate 2 to the input of gate 4 and the output of gate 4 to the input of gate 2. lb) Fig. 77. Set-reset (SR) flip-flop. In order to understand fully the operation of a basic SR flip-flop, it is necessary to look first at its NAND gate equivalent (Fig. 17(b)). Assume initially that both the S and R inputs are at Logic 0 and therefore the outputs of the two inverters, gates 1 and 3, must be Logic 1. If the Q output is initially assumed to be at Logic 0, then the two inputs to NAND gate 4 will be a Logic 1, from inverter 3, and a Logic 0, as a feedback signal from the output Q. The output from NAND gate 4, the Q output, must therefore be a Logic 1. As a result, the inputs to NAND gate 2 will be a Logic 1 from inverter 1 and a Logic 1 as a feedback signal from the Q output. The output from NAND gate 2 must therefore be at Logic 0, the value initially assumed for Q. The circuit will remain in this stable condition until either the d.c. power is re-moved or the input signals are changed. If input S is now changed from Logic 0 to Logic 1, the output from inverter 1 must fall to Logic 0, which will immediately change the Q output from NAND gate 2 to a Logic 1.
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