Computer Science
RISC Processor
A RISC (Reduced Instruction Set Computer) processor is a type of microprocessor that emphasizes a small, highly optimized set of instructions, which allows it to execute simple instructions in a single clock cycle. This design approach aims to improve performance by simplifying the processor's instruction set and focusing on executing instructions quickly. RISC processors are commonly used in embedded systems and mobile devices.
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10 Key excerpts on "RISC Processor"
No longer available |Learn more- (Author)
- 2014(Publication Date)
- Learning Press(Publisher)
________________________ WORLD TECHNOLOGIES ________________________ Chapter 6 Reduced Instruction Set Computing and Direct Memory Access Reduced instruction set computing Reduced instruction set computing , or RISC is a CPU design strategy based on the insight that simplified (as opposed to complex) instructions can provide higher performance if this simplicity enables much faster execution of each instruction. A computer based on this strategy is a reduced instruction set computer (also RISC ). There are many proposals for precise definitions, but the term is slowly being replaced by the more descriptive load-store architecture . Well known RISC families include DEC Alpha, AMD 29k, ARC, ARM, Atmel AVR, MIPS, PA-RISC, Power (including Power-PC), SuperH, and SPARC. Some aspects attributed to the first RISC-labeled designs around 1975 include the observations that the memory-restricted compilers of the time were often unable to take advantage of features intended to facilitate manual assembly coding, and that complex addressing modes take many cycles to perform due to the required additional memory accesses. It was argued that such functions would be better performed by sequences of simpler instructions if this could yield implementations small enough to leave room for many registers, reducing the number of slow memory accesses. In these simple designs, most instructions are of uniform length and similar structure, arithmetic operations are restricted to CPU registers and only separate load and store instructions access memory. These properties enable a better balancing of pipeline stages than before, making RISC pipelines significantly more efficient and allowing higher clock frequencies. Non-RISC design philosophy In the early days of the computer industry, programming was done in assembly language or machine code, which encouraged powerful and easy-to-use instructions. CPU desig-ners therefore tried to make instructions that would do as much work as feasible.
- F Baiardi, Tadao Ichikawa, L Lapriore(Authors)
- 1992(Publication Date)
- World Scientific(Publisher)
Definitions of RISCs There are many definitions of a RISC [14, 15] and they vary with time. Colwell proposes the following as a working definition of a RISC [13]: 1. Single-cycle operation: This simplifies the control logic such as pipelining and •Originally presented with the title: Reduced Instruction Set Computers (© 1985 ACM. Reprinted, with permission, from Communication of [he ACM. Vol.28. No.l. pp. 8-21, 1985). 121 122 Reduced Architecture interruption, and facilitates rapid execution. 2. Memory access only by the load/store instructions: This simplifies the instruction set and hardware, and reduces cycle-time. 3. Hardwired control logic: This provides the fastest possible single-cycle operation. 4. Relatively few instructions and addressing modes: This facilitates a fast, simple interpretation by the control engine. 5. Fixed instruction format: This eases the hardwired decoding of instructions. 6. More compile-time effort: Static run-time complexity must move into the compiler meaning that an optimizing compiler is inevitable for a RISC. Tabak presents the following eight points as the characterizationof RISCs [ 14]: 1. Smaller number of machine-language instructions. 2. Smaller number of addressing modes. 3. Smaller number of instruction formats, 4. Single sycle execution of all or most instructions. 5. Memory access by load/store instructions only. 6. Larger number of user's general-purpose CPU registers. 7. Hardwired control. 8. Support of high-level languages. He then looked over twelve systems about whether they satisfied the above points. The result is shown in the following table. The first four systems in the table are experimental prototypes and the rest are commercial systems.
eBook - PDFMicroprocessor Architectures and Systems
RISC, CISC and DSP
- Steve Heath(Author)
- 2014(Publication Date)
- Newnes(Publisher)
Instead of using them, their operation was synthesized from sequences of simpler instructions. This has another implication: if only the simpler instructions are The RISC challenge 73 required, the processor hardware required to implement them could be reduced in complexity. It therefore follows that it should be possible to design a more performant processor with less transistors and less cost. With a simpler instruction set, it should be possible for a processor to execute its instructions in a single clock cycle and synthesize complex operations from sequences of instructions. If the number of instructions in a sequence, and therefore the number of clocks to execute the resultant operation, were less than the cycle count of its CISC counterpart, higher performance could be achieved. With many CISC processors taking ten or more clocks per instruction on average, there was plenty of scope for improvement. The initial RISC research The computer giant IBM is usually acknowledged as the first company to define a RISC architecture in the 1970s. This research was further developed by the Universities of Berkeley and Stanford to give the basic architectural models. RISC can be described as a philosophy with three basic tenets: 1 All instructions will be executed in a single cycle This is a necessary part of the performance equation. Its implement- ation calls for several features: the instruction op code must be of a fixed width which is equal to or smaller than the size of the external data bus, additional operands cannot be supported, and the instruction decode must be simple and orthogonal to prevent delays. If the op code is larger than the data width or additional operands must be fetched, multiple memory cycles are needed, increasing the execution time. 2 Memory will be accessed only via load and store instructions This naturally follows from the above. If an instruction manipulates memory directly, multiple cycles must be performed to execute it.
eBook - PDF- Florence Slater(Author)
- 1992(Publication Date)
- Academic Press(Publisher)
RISC will also migrate downward, in versions designed to operate at slower clock speeds and without cache memory support. Some of the silicon saved by the simpler instruction decoder can be used to simplify the system-level hardware design, making RISC chips more attractive for embedded control. 2 Instruction Set Design Brian Case Marketing hoopla behind the promotion of RISC architectures has been criticized, and it may seem that most of the popular press radi-ates more heat than light. The key issues in the RISC versus CISC comparison are the interactions between computer architecture, com-puter implementation, and compiler technology, and the astonishing synergy that can result from good design. RISC is both hardware and soft-ware. While it is true that RISC stands for Reduced Instruction Set Computer, the point of the RISC philosophy is not simply the reduction of the number of instructions. RISC was chosen because it is a catchy name and because one of the most apparent attributes of the first publicized RISC instruction sets was the dramatically smaller number of instructions. Hav-ing a small number of instructions is not important, however; what is important is the nature of the instructions. RISC Instructions Allow Uniform Pipelines The people who promote RISC architectures apparently believe that the instruction set is fundamental to improved performance. I, personally, want you to believe it because it is the truth. The instruction set has a first-order impact on performance simply because hardware must some-how implement the semantics of the instructions. 12 2. Instruction Set Design 13 Everyone knows the two ways to improve the performance of a com-puter: (1) speed up the clock 1 and (2) use parallelism.
eBook - PDF- Alvin Albuero De Luna(Author)
- 2023(Publication Date)
- Arcler Press(Publisher)
So, the following CISC assembly pseudocode (Garth, 1991; Vanhaverbeke and Noorderhaven, 2001): becomes the following RISC pseudocode: The resultant code is larger, but the instruction decodes the unit’s decreased complication may lead to speedier overall functioning. To provide RISC its ease, many similar code optimizations occur (Krad and Al-Taie, 2007). RISC Processors are distinguished by a variety of features. They feature enormous register sets (over 1,000 in certain designs), minimizing the number of times the CPU needs to reach the main memory. Variables that are often used may be stored in the CPU, minimizing the number of requests Dissecting Computer Architecture 18 to (slow) exterior memory. This is used by high-level language compilers (like C) to maximize processor efficiency (El-Aawar, 2006). RISC computers provide quick instruction execution due to their smaller and easier instruction decode units, which also minimizes the area and energy usage of the processing element. RISC instructions are typically executed in one and otherwise two cycles (it largely depends on the specific processor) (Wolfe and Chanin, 1992). It’s in comparison to commands for a CISC processor, which might consume tens of cycles to complete. On an 80486 CISC processor, for instance, one instruction (integer multiplication) requires 42 cycles to accomplish. On a RISC CPU, a similar instruction may only require one cycle. A RISC Processor’s instructions follow a basic format. The duration of all instructions is often similar (which provides instruction to decode units easier) (Tokhi and Hossain, 1995). The “load/store” architecture is implemented by RISC Processors. This implies that store and load are the only instructions that make use of memory. A CISC processor, on the other hand, allows many (if not all) instructions to reach or change memory. All the other instructions (this apart from store and load) on a RISC Processor task only on the registers.
eBook - PDF- Aharon Yadin(Author)
- 2016(Publication Date)
- Chapman and Hall/CRC(Publisher)
Despite the inherent advantages in the RISC technology, it took quite some time before it was widely implemented in commercial systems. One of the reasons was the lack of soft-ware suited for the technology. Significant performance gains were achieved by sophisti-cated compilers that optimize the code to the architecture. Using a nonfitted compiler will not provide the anticipated benefits. Instruction-Level Parallelism One of the important principles of the RISC technology is the fixed duration execution instructions, because this feature enables parallelism on the single instruction level. The parallelism is made possible by using a pipeline mechanism that splits the single instruc-tion into its microinstructions and executing these in parallel. As already stated, each instruction when executed is split into several distinct stages as described by Figure 4.27 . • Compute the instruction’s address. This is necessary when the instruction occupies a different number of bytes or when the previous instruction was a branch. • IF: Instruction fetch which brings the instruction from memory into the CPU. • ID: Instruction Decode including determining the instruction’s operands. • Compute operand addresses. After the instruction was decoded, it is possible it addresses some memory resident variables. This stage calculates the addresses of these operands. Central Processing Unit ◾ 151 • Operands fetch which brings the operands from memory or registers. • Execute the instruction. • Compute the results address. • Write back to store the result into its destination. Then, it starts all over again for the next instruction. To simplify the issue and to better explain the principle of pipelining, we will assume a pipeline with four stages. Therefore, in this specific case each instruction is split into: • IF: Instruction Fetch, which brings the instruction from memory into the CPU. • ID: Instruction Decode, including fetching all the instruction’s operands.
eBook - ePub- Jim Ledin, Dave Farley(Authors)
- 2022(Publication Date)
- Packt Publishing(Publisher)
V represents the Roman numeral five.The RISC-V project began as a clean sheet with several major goals:- Design a RISC instruction set architecture (ISA ) suitable for use across a wide spectrum of applications, from micro-power embedded devices to high-performance cloud server multiprocessors.
- Provide an ISA that is free to use by anyone, for any application. This contrasts with the ISAs of almost all other commercially available processors, which are the carefully guarded intellectual property of the company that owns them.
- Incorporate lessons learned from previous decades of processor design, avoiding wrong turns and suboptimal features that other architectures must retain in newer generations to maintain compatibility with previous, sometimes ancient in technological terms, generations.
- Provide a small but complete base architecture suitable for use in embedded devices. The base ISA is the minimal set of capabilities any RISC-V processor must implement. The base RISC-V is a 32-bit processor with 31 general-purpose registers. All instructions are 32 bits long. The base ISA supports integer addition and subtraction but does not include integer multiplication and division. This avoids forcing minimal processor implementations to include relatively expensive multiplication and division hardware for applications that do not require those operations.
- Provide optional ISA extensions to support floating-point mathematics, atomic memory operations, and multiplication and division.
- Provide additional ISA extensions to support privileged execution modes, similar to the x86, x64, and ARM privileged implementations discussed in Chapter 10 , Modern Processor Architectures and Instruction Sets .
- Support a compressed instruction set, implementing 16-bit versions of many 32-bit instructions. In processors implementing this extension, 16-bit instructions may be freely interspersed with 32-bit instructions.
eBook - ePubComputer Architecture
Software Aspects, Coding, and Hardware
- John Y. Hsu(Author)
- 2017(Publication Date)
- CRC Press(Publisher)
IA-64 is a powerful engine for compute bound jobs for three reasons. First, it has extensive parallel operations. Second, it has fewer branches. Third, it has no register saving and restoring during subroutine linking. Nevertheless, if applications are I/O bound such as Web searches, games, and word processing, the IA-64 may not greatly impact the speed. There are other debatable issues. First, branch conditions always exist in a computer, e.g., looping, call, return, and interrupt. If we somehow design a CPU in such a way that the same time is spent to execute a branch; conditional or unconditional, we simply flush the instruction pipe. Second, during context switching the three extensive register sets cause too much overhead. In fact, some applications do not need a large register set. In addition, if the L1 cache size is reduced, it can match the speed of registers because both are on-chip. Third, a large code size slows down loading and transmission. Hence, we explore a new processor design from a different angle.9.4 REDUCED SOFTWARE SOLUTION COMPUTER
The acronym RssC (pronounced arsk) stands for reduced software solution computer, which has an enhanced architecture derived from mainframes.1,5,78 The machine supports four explicit segments without paging. The size of each segment can be up to 1 GB and the processor has multiple execution units. It is designed for real-time applications that include DSP (digital signal processor) applications.36,81 The machine supports floating point arithmetic via a microcode sequence. For scientific applications, a vector math unit can be added. In addition, many clusters can be interconnected, and each cluster has many CPUs sharing one memory. Such a system qualifies as a supercomputer system. The application program running on one CPU can place messages in shared memory for the other CPUs in the same cluster to interpret and execute.The RssC machine supports 32 GRs (general registers) and 16 of them can be used as index registers. Some registers are designated for special functions, e.g., some are reserved for branch or floating point operations. Because each functional unit has a different speed, an instruction can be dispatched out of order. In other words, the CPU is a decoupled pipe. The machine supports an instruction queue in addition to an instruction cache so the instruction retrieval time can be reduced.
eBook - PDFComputer Architecture
Fundamentals and Principles of Computer Design, Second Edition
- Joseph D. Dumas II(Author)
- 2016(Publication Date)
- CRC Press(Publisher)
List and explain nine common characteristics of RISC architectures. In each case, discuss how a typical CISC processor would (either completely or partially) not exhibit the given attribute. 9. How does the overlapping register windows technique, used in the Berkeley RISC and its commercial successor the Sun SPARC, sim-plify the process of calling and returning from subprograms? Chapter four: Enhancing CPU performance 237 10. You are on a team helping design the new Platinum V ® processor for AmD e l Corporation. Consider the following design issues: a. Your design team is considering a superscalar versus superpipe-line approach to the design. What are the advantages and disad-vantages of each option? What technological factors would tend to infuence this choice one way or the other? b. Your design team has allocated the silicon area for most of the integrated circuit and has narrowed the design options to two choices: one with 32 registers and a 512-KB on-chip cache and one with 512 registers but only a 128-KB on-chip cache. What are the advantages and disadvantages of each option? What other factors might infuence your choice? 11. How are VLIW architectures similar to superscalar architectures, and how are they different? What are the relative advantages and disadvantages of each approach? In what way can VLIW architec-tures be considered the logical successors to RISC architectures? 12. Is explicitly parallel instruction computing (EPIC) the same thing as a VLIW architecture? Explain why or why not. 13. Are superthreaded and hyperthreaded processors the same thing? If not, how do they differ? 14. Fill in the blanks below with the most appropriate term or concept discussed in this chapter: The time required for the frst result in a series of com-putations to emerge from a pipeline. This is used to separate one stage of a pipeline from the next. Over time, this tells the mean number of operations completed by a pipeline per clock cycle.
eBook - PDF- S. A. Money(Author)
- 2014(Publication Date)
- Academic Press(Publisher)
6 RISC TYPE PROCESSORS This page intentionally left blank ACORN MACHINE ACORN RISC MACHINE (ARM) PROCESSOR This processor was developed by Acorn Computers for use in their Archimedes personal computers and in graphics workstations based upon this machine. The CPU uses the reduced instruction set (RISC) principle to enable most instructions to execute in one cycle to provide program execution rates of the order 4 to 5 million instructions per sec (MIPS). The CPU in fact forms part of a chip set which includes devices for memory and display management and for parallel and serial I/O channels. Each of the chips in the set was produced by using programmed logic arrays designed by VLSI Technology Inc who manufacture the chips for Acorn. The ARM processor would normally be used with the VL86C110 Memory Controller to provide a machine capable of multi-tasking and multi-user operation with a virtual memory of up to 32 Mbytes and a physical memory of up to 4 Mbytes. A newer version of this processor has recently been developed by Acorn and this is expected to provide a significant increase in the effective processing speed to around 10 MIPS. This processor is particularly useful for high speed computation intensive tasks such as image processing and complex real time controller systems. It might also be applicable for embedded processor applications such as in laser printer control. In general a system would be built up using the four chip set comprising the VL86C010 processor, VL86C110 MMU, VL86C310 display con- troller and a VL86C410 I/O interface chip. These are all implemented using CMOS to provide low power operation. Prime manufacturer VLSI Technology Inc at 0 with bits 2-25 coming from the PC register to produce a 26-bit address and giving a nominal 64 kbyte address space.
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