Exclusive or Operation

6 Key excerpts on "Exclusive or Operation"

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  eBook - PDF

  Digital Logic

  With an Introduction to Verilog and FPGA-Based Design

  • M. Rafiquzzaman, Steven A. McNinch(Authors)
  • 2019(Publication Date)
  • Wiley

    (Publisher)

  72 Digital Logic with an Introduction to Verilog and FPGA-Based Design Finally, Exclusive-OR is commutative and associative: A ⊕ B = B ⊕ A (A ⊕ B) ⊕ C = A ⊕ (B ⊕ C) = A ⊕ B ⊕ C The Exclusive-NOR operation among three or more variables is called an “even function” because the Exclusive-NOR operation among three or more variables includes product terms in which each term contains an even number of 1’s. For example, consider Exclusive-NORing three variables as follows: ƒ = A ⊕ B ⊕ C = (AB + AB) ⊕ C Let D = AB + AB. Then D = AB +AB = AB + A B. Hence, ƒ = D ⊕ C = DC + D C = (AB + AB)C +(AB + A B)C Hence, ƒ = ABC + ABC + ABC + A B C. Note that in this equation, ƒ = 1 when one or more product terms in the equation are 1. However, by inspection, the binary equivalents of the right-hand side of the equation are 101, 011, 110, and 000. That is, the function is expressed as the logical sum (OR) of product terms containing even numbers of ones. Therefore, the function is called an even function. Similarly, it can be shown that Exclusive-OR operation among three or more variables is an odd function. Exclusive-OR or Exclusive-NOR operation can be used for error detection and correction using parity during data transmission. Note that parity can be classified as either odd or even. The parity is defined by the number of 1’s contained in a string of data bits. When the data contains an odd number of 1’s, the data is said to have “odd parity”; on the other hand, the data has “even parity” when the number of 1’s is even. To illustrate how parity is used as an error check bit during data transmission, consider Figure 3.25. Suppose that Computer X is required to transmit a 3-bit message to Computer Y. To ensure that data is transmitted properly, an extra bit called the parity bit can be added by the transmitting Computer X before sending the data. In other words, Computer X generates the parity bit depending on whether odd or even parity is used during the transmission.

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  Reliability of Computer Systems and Networks

  Fault Tolerance, Analysis, and Design

  • Martin L. Shooman(Author)
  • 2003(Publication Date)
  • Wiley-Interscience

    (Publisher)

  for POS designs and NOR gates for SOP designs. For more details, see the following references: Hill [1981], Kohavi [1978], Mano [1995], Roth [1995], Shiva [1988], Wakerly [2001]. C5.4 EXOR The standard OR gate has an output equal to one whenever either of the inputs has an input of one or both inputs are one. An exclusive OR function (EXOR) has an output equal to one whenever either of the inputs has an input of one but not when both inputs are one. The switching function can be written as f (x, y) = xy′ + x′ y. This function has a special logic symbol written as f (x, y) = x ⊕ y. The EXOR function occurs frequently in coding theory and in other COMBINATORIAL CIRCUITS 491 application areas. It is easy to recognize in a K map by its “checkerboard” pattern of ones and zeroes. In shorthand notation, f (x, y) = 10 + 01 = m(1, 2); for three and four variables, f (x, y, z) = xy′ z′ + x′ yz′ + x′ y′ z + xyz = 100 + 010 + 001 + 111 = m(0, 1, 2, 4, 7); f (w, x, y, z) = wx′ y′ z′ + w′ xy′ z′ + w′ x′ yz′ + w′ x′ y′ z + wxyz′ + wxy′ z + wx′ yz + w′ xyz = 1000 + 0100 + 0010 + 0001 + 1110 + 1101 + 1011 + 0111 = m(0, 1, 2, 4, 7, 8, 11, 13, 14). Note that one of the properties of the EXOR function is that in the binary notation, each minterm has an odd number of ones. The function is used extensively in Chapter 2 on coding. C5.5 IC Chips Several courses in electrical engineering curricula study in detail the features of integrated circuits (also called ICs or “chips”); however, for our purposes, we need to know a few facts. Integrated circuits come in a wide variety of device types or families that vary in switching speed, power consumption, immunity to noise and cost, and other factors.

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  Principles Of Computer Programming NQF3 SB

  TVET FIRST

  • S Sasti D Sasti(Author)
  • 2019(Publication Date)
  • Macmillan

    (Publisher)

  Exclusive OR (XOR) gate Let’s look at an example. Example 1.7: Combinations of logic gates Scenario You are at a party and there are limited seats available. You can either sit or you can stand at the party. Is it possible to do both? No. Let’s look at the truth table for this problem where A represents being seated and B represents standing. Table 1.10: Truth table for XOR gate A B Output 0 0 0 0 1 1 1 0 1 1 1 0 The only time the result will be true is if one condition is TRUE and the other is FALSE. This is the logical operator XOR. Boolean expression (A AND NOT(B)) OR (NOT(A) AND B) Logic circuit A B Q Figure 1.7: XOR gate logic circuit [ ¹ 15 min] 14 Topic 1 Example 1.7: Combinations of logic gates (continued) The XOR logic gate replaces the logic circuit in Figure 1.7. The XOR operator has its own symbol shown in Figure 1.8. A Q B Figure 1.8: XOR symbol Unit 1.6: Principles of logic devices 1.6.1 Logic devices and symbols So far, we have considered only fairly simple logic devices. Other useful logic circuits that are used in complex electronic devices include: l Flip-flops or multivibrators. l Registers and shift registers. l Counters. These logic devices are different from the simpler logic gates because they can remember their previous logic state. This ability allows flip-flops, for instance, to be cascaded together to form binary counters. These devices are integrated circuits (ICs) and all look much the same. They are identified in circuit diagrams by standard symbols and model numbers. Armed with this information, you can easily look up each component in the manufacturer’s catalogue to see what it does and how its contact pins are connected internally. 1.6.2 Operations using logic devices The logic devices you have learned about so far have all been stateless. This means that what they do next does not depend on their previous actions. That is, they have no memory of what has happened previously.

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  eBook - ePub

  The Logician and the Engineer

  How George Boole and Claude Shannon Created the Information Age

  • Paul Nahin, Paul J. Nahin(Authors)
  • 2012(Publication Date)
  • Princeton University Press

    (Publisher)

  And second, if there were actually two errors in the received bits (or more generally any even number of errors), then the parity bit comparison at the receiver will incorrectly say all is okay. A diagram like Figure 7.1.2 is very nice for a high-level, slide-show management meeting (I call it a Jobs-diagram, in honor of Apple’s late marketing genius Steve Jobs, who sold a good line, but who I suspect might have been more than just a little vague on what is actually inside an Apple computer or iPad). For engineers who are tasked with building real hardware, however, it really won’t do. What we need to do now is show precisely how to build both the parity bit generator logic at the source end of the channel, and the parity bit checking logic at the receiver end of the channel. What we are aiming for is a Wozniak-diagram (in honor of Apple’s Steve Wozniak, the technical brains behind the original Apple computer). 7.2 THE EXCLUSIVE-OR GATE (XOR) To lay the groundwork for parity logic, this section introduces a “new” logic gate, the exclusive-OR (written as XOR). It isn’t actually really new, since it can be built from either NOR or NAND gates, but the XOR is such a useful function that it is usually treated as deserving a basic logic gate in its own right. If A and B are Boolean variables, then f = A ⊕ B is the exclusive-OR of A and B —take a look back at (4.3.5)—and its logic circuit symbol is shown in Figure 7.2.1. Unlike the other logic gates we’ve discussed, the XOR always has just two inputs. The construction of the XOR of A and B using just NOR gates is shown, and the circuit should make sense if you write (recall De Morgan) How to build the XOR from AND, OR, and NOT gates should be obvious. Before continuing with the parity discussion of the last section and how the XOR comes into play, let me digress for just a bit here and show you a fundamental application of the XOR in a completely different setting

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  eBook - ePub

  Electronic Logic Circuits

  • J. Gibson(Author)
  • 2013(Publication Date)
  • Routledge

    (Publisher)

  Table 2.14 .

  Table 2.14

  The exclusive-OR function is often indicated by the symbol in equations. Hence,

  R = A B

  Although the exclusive-OR function is only defined for two inputs, an equation such as X = A B C D is exact because the same result is obtained whichever order the exclusive-OR operations are performed in. That is (A B) (C D) gives exactly the same result as ((A B) C) D. These multiple-input systems are not called exclusive-OR gates; this name is only applied to the two-input gate.

  Fig. 2.9 EXCLUSIVE-OR gate symbols

  Some of the circuit symbols for exclusive-OR gates are shown in Fig. 2.9 . The exclusive-OR function is available as an integrated circuit but it is also easily constructed from the standard functions. For example, it can be shown that using NAND gates

  and these NAND gate logic circuits are shown in Fig. 2.10 .

  Fig. 2.10 NAND gate implementations of the EXCLUSIVE-OR function

  2.8 Logic circuit analysis

  Those readers who are familiar with linear electronic circuit analysis will be aware that the analysis process is difficult. In the case of combinational logic circuits, analysis is a trivial (although tedious) task. The aim of any circuit analysis is to start from a circuit diagram and to obtain an exact description of the behaviour of the circuit; when the circuit is a combinational logic one the result of an analysis will be either a Boolean expression or a truth table.

  To perform the analysis it is sufficient to work systematically through the circuit from the inputs to the outputs, determining the output of every gate. Example 2.4

  Fig. 2.11

  Analyse the circuit behaviour of the combinational logic system shown in Fig. 2.11

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  Computer Arithmetics for Nanoelectronics

  • Vlad P. Shmerko, Svetlana N. Yanushkevich, Sergey Edward Lyshevski(Authors)
  • 2018(Publication Date)
  • CRC Press

    (Publisher)

  This property is efficiently utilized in logic design, especially in design of specific-area applications, in particular, encoding and encryption of information. There are various physical and molecular effects in predictable technology that can be interpreted as EXOR operations. Nanocomputing devices based on these effects can be used in logic network design and implementation. Polynomial forms are well suited to logic with more than two values -so-called multivalued logic. This fact is utilized in the design of some contemporary and next-generation devices. In this chapter, only EXOR polynomial forms are considered. The corresponding algebra is called polynomial algebra in the field GF(2). Other polynomial forms are mentioned in the “Further study” section. Example 9.1 Figure 9.2 shows the EXOR gate and its AND– OR equivalent network. Using the criterion of the number of gates, the AND–NOR implementation is more complicated than EXOR-based networks. 258 Computer Arithmetics for Nanoelectronics f = x 1 ⊕ x 2 f = x 1 x 2 ∨ x 1 x 2 = x 1 ⊕ x 2 x 1 x 2 f EXOR = x 1 ⎯ x 2 x 2 ⎯ x 1 f EXOR FIGURE 9.2 The EXOR function is represented by a two-level network of AND and OR gates (Example 9.1). Similarities between SOP and polynomial forms Given a Boolean function, the SOP expressions can be derived from the standard SOP form of this function using the simplification rules. Given a complete set of minterms, standard SOP expressions are formed using the correspondence of 1s in the truth vectors and minterms. By analogy, polynomial forms are derived from the correspondence of polarized minterms and nonzero coefficients of the vector of coefficients. The standard, or canonical, SOP and polynomials forms are unique given a Boolean function. The number of terms in canonical SOP and polynomial expressions are equal to 2 n . Noncanonical SOP expressions can be derived from canonical SOP forms.

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