2-Bit Adder
A 2-bit adder is a digital circuit that adds two 2-bit binary numbers. It consists of logic gates that perform the addition operation, including XOR gates for the sum and AND gates for the carry. The output of the 2-bit adder provides the sum of the two input binary numbers along with a carry out bit.
8 Key excerpts on "2-Bit Adder"
eBook - ePub- Brian Holdsworth, Clive Woods(Authors)
- 2002(Publication Date)
- Newnes(Publisher)
...A 4-bit binary adder is to be used as the basic building block in conjunction with any other logic gates required. 12.7. The decimal digits are to be represented by the 2421 self-complementing code. Develop an algorithm for adding together any two decimal digits using this code. With the aid of this algorithm, design a single stage 2421 adder/subtractor circuit. A 4-bit binary adder is to be used as the basic building block in conjunction with any other necessary logic gates and/or MS1 chips. 12.8. An arithmetic circuit has two selection signals, S 0 and S 1. The circuit is required to perform the operations listed below. Using a 4-bit adder as the basic building block, design the circuit that will implement the above operations. 12.9. Design a binary multiplier that multiplies a 4-bit number, B 3 B 2 B 1 B 0, by a 3-bit number A = A 2 A 1 A 0. The circuit is to be implemented using AND gates and full adders. 12.10. A parallel binary multiplier for 4-bit positive numbers, using the shift and add technique, is illustrated in Figure P12.10. The multiplier is controlled from the box labelled ‘Control logic’ in the diagram. The inputs to the controller are (a) the clock signal X, (b) the start signal N, and (c) the multiplier bit M. The outputs from the controller are (a) the shift pulse S, (b) the add pulse A, and (c) the reset pulse r. Figure P12.10 The control logic is to be designed such that if the multiplier bit, M, is 1 at a given clock time, addition takes place. The multiplier bit should then be reset to 0 and at the next clock time a shift takes place. Using synchronous sequential design techniques, develop the control logic for the multiplier. 12.11. Design a serial binary multiplier using Booth’s method. 12.12. Calculate the product (-9 10) × (-13) 10 using Booth’s algorithm....
eBook - ePub- J. Crowe, Barrie Hayes-Gill(Authors)
- 1998(Publication Date)
- Butterworth-Heinemann(Publisher)
...We now consider the advantages and disadvantages of this type of circuit: • Advantages: • Any combinational logic function can be realised as a two-level circuit. • This is theoretically the fastest implementation since signals have only to propagate through two gates. 2 • They can be implemented in a variety of ways, e. g. AND-OR, OR-AND, etc. • Disadvantages: • A very large number of gates may be required. • Gates with a prohibitively large number of inputs may be needed. • Signals may be required to feed to more gates than is possible (because of the electrical characteristics of the circuit). • The task of minimisation increases exponentially with the number of input variables (although computer programs can obviously help reduce this problem). The effect of minimising a fundamental two-level circuit is to reduce the first three disadvantages although it cannot be guaranteed to remove them. Note that the second disadvantage can always be overcome by using more gates (e. g. by using three two-input AND gates to implement a four-input AND gate) but that this means a single-level gate has itself become a two-level circuit. 4.2.2 Specification for the four-bit binary adder A four-bit binary adder is required to add together two four-bit binary numbers plus one carry-in bit, and produce a four-bit sum plus a carry-out bit. This is shown diagramatically in Fig. 4.14. Fig. 4.14 Block diagram of a four-bit adder By definition this is a combinational logic problem as no memory is involved, and the outputs (the sum and carry-out) depend solely upon the inputs. The truth table for this circuit will have nine input columns, and hence 2 9 = 512 rows, and five output columns. We will now look at four different ways this four-bit adder could be constructed...
eBook - ePubMicroprocessor and Microcontroller Interview Questions:: A complete question bank with real-time examples
A complete question bank with real-time examples
- Anita Gehlot(Author)
- 2020(Publication Date)
- BPB Publications(Publisher)
...A half adder performs the addition of two inputs, and it produces two outputs namely sum and carry. In the truth table, A and B is termed as inputs while the outputs sum and carry are named as S and C respectively. Block diagram: Circuit diagram: Truth table: Input Output A B Sum Carry 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 Boolean expression: Sum = A’B + AB’ Carry = AB Full Adder Full adder performs addition operation when the augend and addend number contain more than 2 digits. The carry obtained from the addition of 2 bits is added to the next higher pair of significant bits. Here, the addition operation involves 3 bits, which are augend bit, addend bit and carry bit respectively. The outputs of the full adder are also referred as sum and carry. Block diagram: Circuit diagram: Truth Table: Input Output A B X S C 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Encoder and Decoder Encoder An encoder is a combinational circuit that converts binary information in the form of a 2N input lines. into N output lines, which represent N bit code for the input. For simple encoders, it is assumed that only one input line is active at a time. Decoder Decoders are digital ICs which are used for decoding. In other words, the decoders decrypt or obtain the actual data from the received code, i.e. convert the binary input at its input to a form, which is reflected at its output. It consists of n input lines and 2^n output lines. A decoder can be used to obtain the required data from the code or can also be used for obtaining the parallel data from the serial data received. Multiplexer and Demultiplexer Multiplexer Multiplexer means many into one. A multiplexer is a circuit used to select and route any one of the several input signals to a signal output. A simple example of a non-electronic circuit of a multiplexer is a single pole multi position switch. Multi-position switches are widely used in many electronics circuits...
eBook - ePub- John Stonham(Author)
- 2017(Publication Date)
- CRC Press(Publisher)
...If bit b i, of the multiplier is 0 2 then the multiplication A × b i must be zero for all possible values of A. If b i is 1 2 then the multiplication A × b i is equal to A. Therefore no extra logical operation or calculation is required in this step of the algorithm. Binary multiplication is therefore only a series of shift-and-add operations and like the subtractor operation, this too can be implemented based on an adder circuit, enhanced with three data stores and a control unit. A block diagram of a binary multiplier is shown in Fig. 7.7. Fig. 7.7 A binary shift-and-add multiplier. For example, parallel or look-ahead-carry adder. The binary adder is the main processor in a multiplier. It can be a ripple-through-carry type or one of the faster adders previously described. The adder resolution needs to be 2 n bits as the data in register A (the multiplicand) and register B (the multiplier) are n bits. Owing to the increased complexity of the system, a controller unit is necessary to schedule the flow of information. The controller receives the least significant bit b 0 from register B via its input K. If b 0 is 0, register A is shifted 1 bit left initiated by control signal C 2 and register B is shifted 1 bit right through C 3. If, however, b 0 is 1 then the contents of register A and the accumulator are input to the adder via controls C 1 and C 4 and the resulting addition stored in the accumulator before the shift controls are applied to registers A and B...
eBook - ePub- Herbert L. Blitzer, Karen Stein-Ferguson, Jeffrey Huang(Authors)
- 2010(Publication Date)
- Academic Press(Publisher)
...Thus, the circuit diagram of half adder can be expressed as shown in Figure 12.16. Table 12.8 Truth Table of a Full Adder A half adder can handle only the addition of two single digits but not enough to compute the addition of two multiple-bit binary values because a half adder does not have an additional input line “carrying in” a possible carry value. A full adder is the circuit that is extended from two half adders and can add the sum from the half adder to the carry-in bit. The output is a sum bit and a carry-out bit. A full adder circuit can simply be duplicated multiple times for multiple-bit values by simply connecting the carry-out from the lower-bit adder to the carry-in of the next higher-bit adder. Figure 12.17 illustrates the logic diagram of a full adder as well as the truth table. Table 12.7 Truth Table of a Half Adder FIGURE 12.16 The logic diagram of a half adder. FIGURE 12.17 The logic diagram of a full adder. FIGURE 12.18 The logic diagram of a flip-flop based on NOR gate design. Flip-Flop Circuit Digital circuits can feedback the output of a circuit from its current state as the input of the same circuit for the next cycle; that is, the output of the current state is part of the input of the next state. And it is generally synchronized by a clock. This type of circuit is called a sequential circuit, which has the property of retaining bit value or storing digital information if a circuit is designed in large-scale. The R-S latch, which can store only a single bit (0 and 1), is the simplest sample of a sequential circuit, also called a flip-flop circuit. Given two circuit inputs Reset (R) and Set (S), from the name flip-flop, we can immediately get a sense that outputs Q and Q’ of a two-input in a sequent ial circuit actually are always complements of each other. Flip-flop circuits can be designed with either NOR gates or NAND gates...
eBook - ePubSemiconductor Basics
A Qualitative, Non-mathematical Explanation of How Semiconductors Work and How They are Used
- George Domingo(Author)
- 2020(Publication Date)
- Wiley(Publisher)
...We call the module in Figure 11.18 a half adder because it adds only two single‐digit numbers. Basically, they operate on one number at a time. The half adder can be implemented using XOR and AND modules. If the inputs X and Y are 0, the outputs of both the XOR output, V S for signal value and the AND output, V C, for the carry‐on result are 0. The output of the XOR, the third column in the truth table, is 1 only if one of the inputs is 1; otherwise the output is 0. The output of the AND circuit, the fourth column of the truth table, is 1 only if both X and Y are 1. This agrees with the truth table for the sum of two binary numbers, which I show in the fifth column. The symbol for a half adder is just a square box with two inputs, X and Y, and two outputs, V S and V C, with the word “half adder” in the middle of the box for clarity. Figure 11.18 The half adder circuit (left), the truth table (right), and its symbol (lower middle). 11.9 The Full Adder The problem with the half adder is that it can add only two single‐digit numbers, similar to the decimal system limited to adding just two numbers between zero and nine. What happens when we want to add larger numbers like 15 + 3? In addition to the 5 and the 3, we have the digit 1 (which is not 1 but a 10) that we need to include in our sum. In the binary system we have a similar situation. With the half adder we can add 1 + 0 or 1 + 1 but how about 10 to 1? That is when we need the full adder, which I show in Figure 11.19. I am using the same trick I used before. Yes, I could show you the structure of the full adder using CMOS or logic modules, but I can more easily create a full adder by using two half adders and an OR module. Note first that the full adder has three inputs, the two digits X and Y, and the carry‐on digit from a previous operation, C*. The first half adder is exactly the same as the adder I explained in Figure 11.18...
- Ed Lipiansky(Author)
- 2012(Publication Date)
- Wiley-IEEE Press(Publisher)
...We can do better if we do not have to wait for the carry out to travel its way to the carry in (EAC). So the 2’s c omplement version of the adder/ subtractor is presented in Figure 8.24. Note the EAC path, seen for the 1’s complement implementation is now not connected for the 2’s complement implementation. It is important to remember that when using 2’s c omplement arithmetic the carry out has to be ignored. Figure 8.24 2’s Complement 4 -bit binary adder/subtractor. Example 8.8 Draw a block diagram of a 4 -bit 2 ’s complement adder/subtractor that upon its control input being 0 it adds, but if the control input is 1 it subtracts using 2’s complement arithmetic. Equation (8.17) repeated below for the reader’s convenience shows the algorithm used to obtain the 2’s complement of an n- bit binary number (8.29) Figure 8.24 below depicts the solution to Example 8.8. Referring to Figure 8.24 let us see how the adder part works. Upon setting to zero the control input to the select line of the 1-of-2 mux, the overall adder C in is zero and the 1’s complementer logic box is in pass-through mode, i.e. does not invert its inputs. The logic of Figure 8.24 simply adds with a high - level control input. When the control input is zero two things happen, the C in is set to one and the one’s complementer logic box control input is also set to one. The 1’s complementer is set to complement mode and since the C in to the adder/subtractor is set to 1, the logic is basically executing: (8.30) Equation (8.30) in effect performs the subtraction of B from A in 2’s complement form. 8.6 CARRY LOOK AHEAD (CLA) OR FAST CARRY GENERATION Let us now go back to our full-adder basic building block with its two logic equations, repeated below for the reader’s convenience: (8.31) (8.32) Since a basic multi-bit adder can be thought as a concatenation of full-adders, let us generalize Equations (8.31) and (8.32) for a FA slice...
eBook - ePub- J. Gibson(Author)
- 2013(Publication Date)
- Routledge(Publisher)
...Each one of these circuits has its own unique truth table. If n is 2 there are sixteen possible circuits, when n is 3 there are two hundred and fifty-six and so on. The number increases rapidly with n and it would be an uneconomic proposition to manufacture different circuits for every possible case. Fortunately it is possible to choose a set consisting of a small number of basic logic elements and then interconnect several of them to produce a circuit which behaves in the manner required by some specification. There is no unique set of basic logic elements but the five which follow are probably the most useful ones; in addition they directly implement a set of mathematical rules which may be used to describe the behaviour of logic systems. The basic logic elements used in combinational logic systems are usually called ‘gates’ by electronic engineers. This is because one common application is to control the flow of electrical logic signals along some path; the element may be used to allow the signal to pass or may prevent its passage and this action is analogous to opening or closing a gate across a path. 2.2.1 The AND gate This element has a single output and any number of inputs. It is defined as the combinational logic circuit which gives the output 0 unless all the inputs are at the logic 1 level; in this case only the output is 1. This definition is sufficiently precise to allow the truth table of an AND gate to be written down immediately. Table 2.4 is the truth table for a three-input AND gate. Table 2.4 When this element is used as a component in a large system it is convenient to be able to represent it by some quickly recognized symbol; this makes interpretation of circuit diagrams of a network drawn using such symbols relatively simple. Figure 2.3 shows several different symbols which are used to represent an AND gate...
