Computer Science
Full Adder
A full adder is a digital circuit that performs addition on three input bits and produces a sum and a carry output. It is a fundamental building block in digital arithmetic circuits and is used in the design of processors and other computational devices. The full adder is capable of adding two binary numbers along with a carry input from a previous addition.
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eBook - ePubDigital Electronics 2
Sequential and Arithmetic Logic Circuits
- Tertulien Ndjountche(Author)
- 2016(Publication Date)
- Wiley-ISTE(Publisher)
4 Arithmetic and Logic Circuits4.1. Introduction
Arithmetic circuits are essential in the implementation of microprocessors and circuits for digital signal processing.As the complexity of the direct approach (construct a truth table and then derive and simplify the output logic equations) increases with an increase in the size of data, the modular approach is often chosen to implement arithmetic circuits. A given digital circuit is thus implemented by assembling modules that are designed for numbers with small word lengths.Despite the increasing number of arithmetic operations that are becoming routine, most microprocessors only contain circuits for basic operations, such as an adder (or summer), comparator, multiplier and divider. In addition to arithmetic circuits, there is also a need for circuits that can perform bitwise logic and shift operations. One of the main components of a microprocessor, therefore, is the arithmetic and logic unit (ALU), which encases all the circuits required for carrying out operations on digital data.4.2. Adder
Adders are used to perform a large number of digital operations. In spite of the apparent simplicity of an addition operation, there are several approaches to designing adders.4.2.1. Half adder
A half adder (HA) is a circuit that generates the sum, S, and the carry, C, resulting from the addition of two 1-bit numbers, A and B.An example of a simple addition, A + B, is given in Figure 4.1 . The truth table shown in Table 4.1 is constructed by considering bits C and S to be the MSB and LSB in the 2-bit representation of the addition result. The logic equations for the two outputs are given by:[4.1][4.2]Figure 4.1. Example of a simple addition. For a color version of the figure, see www.iste.co.uk/ndjountche/electronics2.zip
eBook - PDFDigital Design Using VHDL
A Systems Approach
- William J. Dally, R. Curtis Harting, Tor M. Aamodt(Authors)
- 2015(Publication Date)
- Cambridge University Press(Publisher)
Thus we can realize a half adder with just these two gates, as shown in Figure 10.1 . To handle a carry input, we require a circuit that accepts three input bits: a , b , and cin (for carry in), and generates a result r that is the sum of these bits. Now r can range from 0 to 3, but it can still be represented by two bits, s and cout (for carry out). A circuit that adds three equally weighted bits together to generate a sum and a carry is called a Full Adder , and a truth table for this circuit is shown in Table 10.2 . A Full Adder circuit is shown in Figure 10.2 . From Table 10.2 , we observe that the sum output has the truth table of a three-input exclusive-or (i.e., the output is true when an odd number of the inputs are true). The carry output is true whenever a majority of the inputs are 10.2 Binary addition 225 Table 10.2. Truth table for a Full Adder a b cin r cout s 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 2 1 0 1 0 0 1 0 1 1 0 1 2 1 0 1 1 0 2 1 0 1 1 1 3 1 1 cin Majority a b s cout FA a b cout s (a) cin (b) Figure 10.2. Full Adder: (a) symbol, (b) logic circuit. true (two or three inputs true out of three), and thus can be implemented using a majority circuit ( Equation ( 3.6 )). The astute reader will have observed by now that adder circuits are really counters. A half adder, or a Full Adder, just counts the number of 1s on its inputs (all inputs are equivalent) and reports the count in binary form on its output. For a half adder the count is in the range of 0 to 2, and for a Full Adder the count ranges from 0 to 3. We can use this counting property to construct a Full Adder from half adders as shown in Figure 10.3 (a). In the figure the numbers in parentheses indicate the weight of a signal. The inputs are all weighted (1). The result output is a binary number with the sum weighted (1) and the carry out weighted (2). Because an adder counts the 1s on its inputs, they should all be of equal weight – otherwise one input would count more than another.
eBook - PDF- Wai-Kai Chen(Author)
- 2003(Publication Date)
- CRC Press(Publisher)
16.3 Serial Adder A serial adder operates similarly to manual addition. The serial adder, at each step, calculates the sum and carry at one bit position. It starts at the least significant bit position (i.e., i = 0) and each successive next step it sequentially moves to the next more significant bit position where it calculates the sum and carry. At the n -th step, it calculates the sum and carry at the most significant bit position (i.e., i = n – 1). In other words, the serial adder serially adds augend X and addend Y by adding x i , y i , and c i at the i -th bit position from i = 0 to n – 1. From the truth table shown in Table 16.1, we have sum bit s i = x i ≈ y i ≈ c i and carry to the next higher bit position c i +1 = x i · y i ⁄ c i ·( x i ⁄ y i ) (also c i +1 = x i · y i ⁄ c i · ( x i ≈ y i )), where “·” is AND, “ ⁄ ” is OR, and “ ≈ ” is XOR, and henceforth, “·” will be omitted. This serial addition can be realized by the logic network, called a serial adder , or bit-serial adder , shown in Fig. 16.2, where its operation is synchronized by a clock. The addition of each i -th bit is done at a rate of one bit per cycle of clock, producing sum bits, s i ’s, at the same rate, from the least significant bit to the most significant one. In each cycle, s i and c i + 1 , are calculated from x i , y i , and the carry from the previous cycle, c i . The core logic network, shown in the rectangle in Fig. 16.2, for this one-bit addition for the i -th bit position is called a Full Adder (abbreviated as FA ). We obtain a logic network for an FA shown in Fig. 16.3 using AND, OR, and XOR gates. A D-type flip-flop may be used as a delay element which stores the carry for FIGURE 16.1 Examples of addition of numbers in two’s complement representation. 16-4 Logic Design a cycle. Full Adders realized in ECL (emitter-coupled logic) are described in Chapter 13. FAs with a minimum number of logic gates are known for different types of logic gates.
eBook - PDF- R. Townsend(Author)
- 2014(Publication Date)
- Butterworth-Heinemann(Publisher)
A somewhat different approach to the problem of fast binary addition has been adopted by the Manchester University Computer Group, and others. With this point of view the adder and the accumulator register are considered as a single combined device in which the objective is to place the result in the register in the shortest time. In the adder for the Atlas computer 11 a special purpose circuit is designed which derives its speed from the fast propagation of the carry signal from the collector to the emitter of a saturated symmetrical transistor. However this technique is no longer suitable for modern integrated circuit technology. The need for high speed binary adders becomes most important on very large and fast computers having word lengths of 50 to 100 bits, in which the carry propagation time with a conventional ripple carry 106 Addition and Subtraction adder has a serious effect on the performance. With the availability of small lookahead adders complete on integrated circuits, it is now worth while to incorporate these in minicomputers. In any case, the speed of integrated circuit logic gates is continually rising, which makes for a very high performance with conventional methods. The lookahead adder seems to be the preferred method for improving speed on modern large machines. Binary Coded Decimal Adders Most modern processors operate with pure binary numbers, but decimal arithmetic units are still of interest in electronic calculators and special purpose devices, such as point of sale cash registers. The decimal numbers are usually represented as a binary code, the commonest being the straightforward BCD or 1248 weighted code. The 'excess 3' code has been widely used in the past, and is still popular in some applications. The rules of binary coded decimal arithmetic with the BCD and 'excess 3' codes have been described in Chapter 4.
eBook - ePub- John Stonham(Author)
- 2017(Publication Date)
- CRC Press(Publisher)
Design of arithmetic processors 7Objectives□ To design logic circuits for arithmetic. □ To examine ways of increasing the speed of arithmetic units. □ To develop a programmable arithmetic unit capable of performing a number of arithmetic calculations. □ To introduce the concept of a programming language.An important application of logic is in an arithmetic unit. Such a device must be capable of being reconfigured to enable it to carry out a range of numerical operations. This ability to carry out many different operations, depending on the problem needing to be solved, leads to the concept of a programmable system – a computer. The main components of an arithmetic unit will be developed in this chapter and a simple system controller will be specified. An elementary programming language for operating this system will be developed.Ripple-through-carry addition
The addition of two binary inputs has already been considered in Chapter 3 . The combinational logic designs for a Full Adder circuit which accepts input bits A and B and generates the sum A plus B, plus any carry-in together with the resulting carry-out, are given in Fig. 3.9 . This Full Adder circuit can only provide the sum of two single-bit inputs – a very limited device. To extend the resolution of the adder, the cells can be cascaded where each cell receives one corresponding bit from each of the two input numbers to be added together and the carry is propagated from cell to cell as shown in Fig. 7.1 .See page 59. Any system must be designed for the worst case – it could happen in practice.Such a system is known as a ripple-through-carry adder because in the worst case each cell produces a carry and each successive cell cannot generate the correct summation until the previous, i.e. lesser significant cell, has generated its carry output. Consider a ripple-through-carry adder of 8-bits resolution, performing the addition A + B whereA = 12710 and B = 110Fig. 7.1
- Subir Kumar Sarkar, Asish Kumar De, Souvik Sarkar(Authors)
- 2014(Publication Date)
- Jenny Stanford Publishing(Publisher)
That is 0 1 1 0 1 1 0 (Since there is a carry, 3 bit addition have to be done which is not possible with half adder. 1.25 Full Adder and Full Subtractor It adds three binary bits at a time. The two binary bits are called augend bit and addend bit and the other bit is called the carry bit from the previous stage (Fig. 1.75). here A = augend bit and B = addend bit Figure 1.74 Logic circuit realization of the functions f 1 = ( M, A, B ) and f 2 = ( M, A, B ) using NAND gate. Figure 1.75 Block diagram of a Full Adder. 70 Combinational Circuits C i –1 = the carry bit generated from the previous stage that is just previous to present stage. So Full Adder circuit has multiple output and this is a multiple output function. The corresponding function of the Full Adder can be verified using the data given in Table 1.21 Table 1.21 Truth table of a Full Adder Decimal Three inputs Two outputs A B C i –1 S C i 0 0 0 0 0 0 1 0 0 1 1 0 2 0 1 0 1 0 3 0 1 1 0 1 4 1 0 0 1 0 5 1 0 1 0 1 6 1 1 0 0 1 7 1 1 1 1 1 First add B with C i –1 and then add it with A to get the final sum and carry indicated by the logical expressions S and C , respectively. S = ∑ m (1, 2, 4, 7) C = ∑ m (3, 5, 6, 7) The sum satisfies XOR logic (odd number of 1s as I/P) S = 1 and even number of 1s S = 0. S = A ⊕ B ⊕ C i –1. Now verify the result with the K map. But none of the cells can be included in group and hence, S = 001 + 010 + 100 + 111 = A – B – C i –1 + A – BC – i –1 + AB – C – i –1 + ABC i –1 (1.30) If we expand Eq. (1), we get Eq. (2). Expanding Eq. (1), we have: S = A ⊕ B ⊕ C i –1 Let u = A ⊕ B Full Adder and Full Subtractor 71 S = u ⊕ C i –1 = u – C i –1 + — uC i –1 (1.31) and u = ( AB ― + ― AB ) (1.32) u A B A B A A A B A B A B ( ) ( ) A + . A + By Demorgan’s theorem we get = + + + AA AB AB BB So, u ― = ― AB – + AB (1.33) Using Eqs.
eBook - PDF- Wai-Kai Chen(Author)
- 2018(Publication Date)
- CRC Press(Publisher)
41 -1 © 2006 by CRC Press LLC 41 Adders CONTENTS 41.1 Introduction ........................................................... 41- 1 41.2 Addition in the Binary Number System .............. 41- 1 41.3 Serial Adder ............................................................ 41- 3 41.4 Ripple Carry Adder ................................................ 41- 4 41.5 Carry Skip Adder ................................................... 41- 7 41.6 Carry Look-Ahead Adder ...................................... 41- 8 41.7 Carry Select Adder ............................................... 41- 10 41.8 Carry Save Adder ................................................. 41- 11 References ........................................................................ 41- 11 41.1 Introduction Adders are the most common arithmetic circuits in digital systems. Adders are used to do subtraction and also are key components of multipliers and dividers, as described in Chapters 42 and 43. There are various types of adders with different speeds, areas, and configurations. We can select an appropriate one which satisfies given requirements. For the details of adders and addition methods, see Refs. 2, 4–6, 12, 15, 17, and 20. 41.2 Addition in the Binary Number System Before considering adders, let us take a look at addition in the binary number system. In digital systems, numbers are usually represented in the binary number representation, although the most familiar number representation to us is the decimal number representation. The binary number representation is with the radix (base) 2 and the digit set {0, 1}, while the decimal number representation is with the radix 10 and the digit set {0, 1, 2,…, 9}. For example, a binary number (i.e., a number in the binary number representation) [1101] represents 1·2 3 + 1·2 2 + 0·2 1 + 1·2 0 = 13, whereas a decimal number (i.e., a number in the decimal number representation) [8093] for example, represents 8·10 3 + 0·10 2 + 9·10 1 + 3·10 0 = 8093.
eBook - ePub- Joseph Cavanagh(Author)
- 2017(Publication Date)
- CRC Press(Publisher)
2 .Table 4.1 Truth Table for a Full Adder for Binary AdditionThe radix complement of binary numbers (2s complement ) is obtained by complementing each bit of the corresponding positive binary number and adding 1 to the low–order bit position. For example, let A = 0001 11002 = +2810 and A’ = 1110 0011 = 1110 0100 = –28. To obtain the value of a negative number count the weight of the 0s and add 1. Examples of addition operations are shown in Table 4.2 , which add two 8-bit positive and negative operands.Table 4.2 Examples of Addition for Two Eight-Bit Signed Operands4.12.1 Full AdderA Full Adder can be designed from two half adders. A half adder adds two operand bits a and b, and produces two outputs sum and carry-out . The truth table for a half adder is shown in Table 4.3 and the equations for a half adder are shown in Equation 4.2 . From Table 4.1 , the equations for the sum and carry-out of a Full Adder are shown in Equation 4.3 . The logic diagram for a Full Adder is shown in Figure 4.1 .(4.2)s u m =a ′b + a b = a ⊕ b c o u t = a b(4.3)c o u n t =a ′b c i n + ab ′c i n + a b c in ′+ a b c i n= a b + ( a ⊕ b ) c i nTable 4.3 Truth Table for a Half AdderAugend (a ) Addend (b ) Carry-out (cout ) Sum 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 Figure 4.1 Logic diagram for a Full Adder using two half adders.The structural design module is shown in Figure 4.2 using built-in primitives. The test bench module and the outputs are shown in Figures 4.3 and 4.4
eBook - PDF- Israel Koren(Author)
- 2018(Publication Date)
- A K Peters/CRC Press(Publisher)
5 FAST ADDITION 5. 1 RIPPLE-CARRY ADDERS The addition of two operands is the most frequent operation in almost any arith-metic unit. A two-operand adder is used not only when performing additions and subtractions, but also often employed when executing more complex oper-ations like multiplication and division. Consequently, a fast two-operand adder is essential. The most straightforward implementation of a parallel adder for two oper-ands ? n_ d, ? n_ 1 • • • , ? ( and r n_ d, r n_ 1 • • • , r ( is through the use of z basic units called Full Adders . A Full Adder (FA) is a logical circuit that accepts two operand bits, say ? z and r z , and an incoming carry bit, denoted by • z , and then produces the corresponding sum bit, denoted by X z , and an outgoing carry bit, denoted by • z Ld . As this notation suggests, the outgoing carry • z Ld is also the incoming carry for the subsequent FA, which has ? z L d and r z L d as input bits. The FA is a combinational digital circuit implementing the binary addition of three bits through the following Boolean equations: X z ) ? z + r z + • z (5.1) where + is the exclusive-or operation, and • z Ld ) ? z • r z + • z • ( ? z + r z ) (5.2) where ? z • r z is the AND operation, ? z n r z , and ? z + r z is the OR operation, ? z V r z . 93 _ FA _ FA _ FA _ FA 94 5. Fast Addition • n • 1 • d ? n r n X n ? 1 r 1 X 1 ? d r d X d ? ( r ( X ( • ( FIGURE 5. 1 A4-bit ripple-carry adder. A parallel adder consisting of FAs for z ) 4 is depicted in Figure 5.1. In a parallel arithmetic unit, all 2 z input bits ( ? z and r z ) are usually available to the adder at the same time. However, the carries have to propagate from the FA in position 0 (the position of the FA whose inputs are ? ( and r ( ) to position 7 in order for the FA in that position to produce the correct sum and carry-out bits.
- Enoch Hwang(Author)
- 2017(Publication Date)
- Cengage Learning EMEA(Publisher)
Again, we will use the ripple-carry adder as the building block and then insert some combinational logic circuitry in front of the two input oper-ands to each Full Adder. This way, the primary inputs will be modified accordingly, FIGURE 4.16 Behavioral VHDL code for a 4-bit adder-subtractor combination component. LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- need this to do + and -ENTITY AddSub IS PORT(S: IN STD_LOGIC; -- select subtract signal A, B: IN STD_LOGIC_VECTOR(3 DOWNTO 0); F: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); Unsigned_Overflow: OUT STD_LOGIC; Signed_Overflow: OUT STD_LOGIC); END AddSub; ARCHITECTURE Behavioral OF AddSub IS SIGNAL TempF : STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN PROCESS(S, A, B) BEGIN IF (S = '0') THEN -- addition TempF <= ('0' & A) + ('0' & B); F <= TempF(3 DOWNTO 0); Unsigned_Overflow <= TempF(4); -- Signed overflow = most significant bit of A'B'F + ABF' Signed_Overflow <= ((NOT A(3)) AND (NOT B(3)) AND (TempF(3))) OR ((A(3)) AND (B(3)) AND (NOT TempF(3))); ELSE -- subtraction TempF <= ('0' & A) -('0' & B); F <= TempF(3 DOWNTO 0); Unsigned_Overflow <= TempF(4); -- Signed overflow = most significant bit of AB'F' + A'BF Signed_Overflow <= ((A(3)) AND (NOT B(3)) AND (NOT TempF(3))) OR ((NOT A(3)) AND (B(3)) AND (TempF(3))); END IF; END PROCESS; END Behavioral; Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-202 130 CHAPTER 4 STANDARD COMBINATIONAL COMPONENTS depending on the operations being performed before being passed to the Full Adder. The general, overall circuit for a 4-bit ALU is shown in Figure 4.17(a) and its logic symbol in Figure 4.17(b). As we can see in Figure 4.17(a), the two combinational circuits above each FA are labeled LE and AE. The logic extender (LE) is for manipulating all logical operations; whereas, the arithmetic extender (AE) is for manipulating all arithmetic operations.
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